D14 Block Diagram (Internal)
Bus Architecture
VD2
VD1
VD3
TE
PDEC
HEVC1
VDO
VCP
HDMI
Link
HDMI
PHY
ADO
H.264
(On2)
FHD
HDMI
PHY
lgm_top
DDR3 PHY (x16)
DDR3 PHY (x32)
1920x2160@60p
DDR3PLL
SSPLL
DCO
DISPLL
1920x2160@60p
Serial/Parallel
TP Stream
HEVC2
Memory Bus Interface (PL301)
lgm_top
DDR3-1600
1Gbit
DDR3-1600
1Gbit
x32
x32
Clock/Reset Gen
Serial Flash
CortexM3
CPU Bus Interface (PL301)
SPI
I2C
Boot
ROM
SRAM ADO MCU0 MCU1 DMA
WDT
UART0
UART1
GPIO
I2C
MCU
RC
H.264
Core1
H.264
Core2
SDRAM
2.5V
(AIP)
LDO
3.3V
(I/O)
LDO
1.1V
(Core)
LDO
1.5V
(DDR3)
LDO
Analog IP
Added : D13
D14
VD0
Deleted : D13
D14
XTAL
(24.75MHz)
DDR3-1600
1Gbit
DDR3-1600
1Gbit
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Only for training and service purposes
LGE Internal Use Only
Summary of Contents for 77EG9700
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