Lexicon MPX G2, Service Manual

Page: 95 / 165

Lexicon
6-17
SHEET 18:
This sheet includes the reset circuit and SRAM battery backup.
During power-up, U43 pin 1 pulls _RESET to ground until the voltage at pin 2 rises above approximately
4.3V. R195 and C208 form a power-on delay. R195 charges C208, which keeps Q20 turned on until its
base reaches Vcc-1.2V. At that point, Q20 turns off, and U43 pin 1 goes to Vcc. This causes _RESET to
go high.
D33 is there to allow a quick response to loss of Vcc. When Vcc slips below 4.3V, D33 is back-biased.
D32 provides a quick discharge path for C208 to allow long resets in the event of short losses of Vcc.
Jumper W3 provides a manual reset.
When Vcc is absent, Q21 is off, and the SRAM's supply voltage (VRAM) comes from the lithium battery. In
order for the SRAM to go into power-down mode, its chip enable pin (WRITE_PROTECT) must be high.
R200 ties WRITE_PROTECT to VRAM.
When Vcc is preset, but _RESET is active, Q21 will be off, which keeps Q22 off as well. This keeps
WRITE_PROTECT high, protecting the SRAM contents until the system is stable.
When Vcc is present and _RESET is off, Q21 is on, which brings WRITE_PROTECT low and turns on Q22,
which couples Vcc to VRAM. D34 keeps Vcc from charging the battery, and R203 adds extra protection to
the battery, as required by some regulating agencies.
Power resistors R113, R114, R116, and R117 are needed to meet the power supply's minimum current
specs.
DETAILS
Power-On Sequence
When +5V comes on from a cold start, it charges C206, and roughly 100 msec later (the timing is not
critical), _RESET goes high. Refer to sheet 18 of the schematic walk-through for a description of the reset
circuit.
The first thing to come out of reset is U45, the FPGA (sheet 4). It has an internal low-voltage detector, so it
starts its initialization phase when Vcc rises above about 2.8V AND _RESET goes high. When the FPGA
enters its initialization phase, it drives ADDR0-ADDR15 and _ROM_EN, and reads roughly 4 Kbytes of
configuration data from the ROM's upper memory. It then performs an error check on the data. If the check
fails, it keeps retrying to reload the data. If there are problems with the EPROM, data, or address busses,
the FPGA will load forever. This is a handy feature, because the FPGA will toggle the address lines,
making it possible to check for shorts and opens in the bus.
During the initialization phase, the FPGA pulls all IO pins to 5V through high-impedance resistors. During
the initialization phase, a roughly 1 MHz clock will appear on pin 74 of U45. If this clock never appears, and
U45 pin 55 (DONE) stays low, U45 is dead.
IMPORTANT NOTE: manually pulling _RESET low (e.g. by shorting W3 on sheet 18) does NOT put the
FPGA into initialization phase. It only resets the states of the flip-flops inside of it. The only way to put the
FPGA into initialization phase is to cycle power.
When the initialization phase finishes, DONE goes high, which brings _RESET1 high, which brings the Z80
out of reset. The Z80 performs power-on diagnostics of the system.
Once the Z80 passes its diagnostics, it gives the bus to the 2186 so that it can perform its own diagnostics.
The two processors pass the bus back and forth until all of the diagnostics are completed. Then the Z80