Lexicon MPX G2, Service Manual

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MPX G2 Service Manual
6-14
SCHEMATIC WALK-THROUGH
SHEET 1:
This sheet shows the Z80 and 2186 wire-ORed onto the data and address busses. As the 2186 doesn't
drive A14 and A15, these lines are pulled high and low, respectively, when the 2186 owns the bus. The
values of R215 and R216 are a compromise to quickly bring the address lines to their correct values once
the Z80 relinquishes the bus and not to pull too hard. The Tau of 2.2K with the 60 pF max capacitance on
A15 is about 130 nsec. This is longer than the shortest time it could take the 2186 to regain the bus. The
solution is to omit A14 and A15 from the decoding equations (where possible) when the DSP owns the bus.
This works as long as the DSP doesn't make an SRAM access too soon after it has acquired the bus.
The relatively sluggish decoding of P15-P17 by the FPGA requires an 80 nsec EPROM.
The SRAM (U54) is made non-volatile by battery BAT1 and associated components (sheet 18).
The worst-case data bus loading is about 90 pF. The worst-case address bus loading is about 85 pF. The
Z80 timings are done with 100 pF loads, so these loads should be acceptable. However, the 2186 timings
are done with 50 pF loads, so I've added extra wait states to the 2186 bus access cycles, to be
conservative.
The two 1N914 diodes and a 2.2K resistor on the EPROM/FLASH are necessary for power on pattern
loading of the FPGA. The RD line is floating when power is first applied, so the diodes provide an active
LOW OE to the EPROM while the FPGA boots. The FPGA signal goes HIGH when it is finished.
The 74HC4053 provides level shifting for the DigiPot control signals to +/- 2.5V.
SHEET 2
Sheet 2 contains the Lexichip and 256K x 20 bits of audio DRAM. The DRAM layout allows for 1M x 4
chips.
SHEET 3:
This sheet contains the display drivers.
The LEDs on the front panel are physically divided into those on the left of the LCD and those on the right.
On the left are two discrete LED's for level meters and three 7-segment displays. On the right are 19
discrete LED's, that are organized as 5 columns of 4 rows. The row-column organization is based on MPX
1. The display and switch matrixes are the same, except that the level meters have been replaced by
discrete level and clipping LED's.
Octal D-flop U74 clocks the IO_DATA bus (a buffered version of the system data bus) on the rising edge of
_DISPLAY_WR1. U74's low three bits are decoded by U69, to create five active-low column select lines.
These are buffered and inverted by switching transistors Q33-Q37. When a selected COL line is driven
high and a ROW line is driven low, the LED at the crosspoint of the col and row will light. Also, if one of the
front panel switches in the selected column is pressed, the SWITCH_ROW signal corresponding it its row
will go high. Resistors R336, R338, R340, R342 and R344 pull non-selected columns to ground, which is
necessary for the proper detection of the switches.
We drive the right row lines directly with U74. We can get away with this because U74 is only driving four
lines, so the total current in the IC remains below 100 mA. However, because we need eight row drivers for
the left display, we use discrete transistors Q25-Q32. The 100-Ohm resistors (R298, etc) limit the row
current to about 28 mA.