Lexicon MPX G2, Service Manual

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Lexicon
6-15
Writing to octal D-flop U72 sets the LCD access mode. The Z80 sets LCD_READ if the next LCD access
will be a read, and clears it if the next access will be a write. The Z80 also sets LCD_ADDR1 if the next
access will be data transfer, and clears it if the next access will be command or status.
The four LSB's of U72, together with resistors R319-R322, form a crude DAC, which controls the LCD
contrast voltage. Most LCD's require a contrast voltage between 0 and 5V, in which case R317 is installed
and R318 is omitted. For those that require negative voltages, R318 is installed and R317 is omitted.
SHEET 4:
Octal transceiver U73 decouples the system data bus from the IO data bus in order to reduce loading on
the system bus. _IOREQ enables the transceiver, and ADDR0 controls the direction. Thus, all odd IO
addresses must be writes, and all even ones reads.
The heart of this sheet is the FPGA, U45. This section will only provide an overview of the FPGA
functionality.
U45 is a Xilinx Field-Programmable Gate Array (FPGA). It consists of a collection of 144 "Configurable
Logic Blocks" (CLB's), each of which resembles a small PAL. The configuration of these CLB's, as well as
the inter-CLB routing, is held in the FPGA's internal SRAM, which is loaded during power-up from the upper
4Kbytes of the EPROM. On power-up, U45 reads the EPROM by driving ADDR0-ADDR15 and _ROM_EN.
Once it is configured, it stops driving the address lines, then brings DONE high, which brings the Z80 out of
reset and gives it control of the bus. The power-up sequence is described later.
U45 performs the following tasks:
ADDRESS DECODING. U45 does some of the address decoding and chip select generation. It creates:
P15-P18, the upper bank addresses for the EPROM,
RAM_A14, the upper address for the SRAM,
_ROM_EN, the EPROM chip select,
_HI_RAM_EN, the chip select for the high byte of SRAM,
_LO_RAM_RD, the read strobe for the low byte of SRAM,
_LO_RAM_WR, the write strobe for the low byte of SRAM,
_LEX_WR, the lexichip write strobe,
_LEX_EN, the lexichip chip select,
LCD_EN, the LCD strobe,
_RD_STATUS, which gates the status registers (U528 and U532, sheet 5) onto the data bus,
_CONTROL_WR, which clocks the addressable latch U518.
Some of the I/O address decoding is at U67, an HC138.
CLOCK GENERATION. U45 divides _MC (512 FS) from the lexichip to make 256FS, 128FS, _128FS,
8FS, FS, and FS_QUAD, which are used by the A/D and D/A converters and the serial link between the
2186 and the lexichip. FS_QUAD is a version of FS, which leads FS by 90 degrees. It is used to mux data
to/from the A/D and D/A converters. RETURN_SCLK is a special narrow-duty-cycle version of 128FS,
which meets the bitclock requirements of the CS5335.
SYNCHRONIZED WORD CLOCK. U45 synchronizes its internally generated word clock (FS) to the
Lexichip's master clock (_MC), to create _LEX_WC.
MIDI UART. U45 contains a stripped-down UART capable of sending and receiving asynchronous data at
31.25 Kbaud. When it receives a byte, it asserts _INT, which interrupts the Z80.
WAIT STATE GENERATOR. U45 decodes Z80 accesses to the Lexichip and LCD, adding two wait states
for Lexichip accesses and four for LCD accesses.