Lexicon MC-1, Service Manual

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Lexicon
5-5
The destructive test is actually 3 tests in one. They include a counter, data write and read test. These tests
do not save the data before writing. Also, more data patterns are written into this section of the SRAM. The
counter test writes a 0 into the first location of memory, a 1 into the next, then a 2, etc. This repeats this
until the volatile section of the SRAM is tested.
The data test of the SRAM writes and reads the volatile section with 55h, AAh, FFh, 00h, 01h, 02h, 04h,
08h, 10h, 20h, 40h, 80h, FEh, FDh, FBh, F7h, EFh, DFh, BFh, and 7Fh. Except for the first the last 16
patterns shift 1's and 0's through the memory locations.
E4 VFD Test
The VFD performs a busy test and a memory test. The busy test is performed by sending information to the
VFD and verifying that the VFD asserts then desserts its busy status. The VFD memory test consists of
writing 55h, and AAh, to the character generator memory and display memory space of the VFD and
reading them back. After the MC-1 has passed the VFD Test, for the rest of the power on diagnostics, the
VFD displays.
E5 Z80 System Interrupt Timer Test
This test checks the system interrupt timer. The PIC 16C54 microprocessor is initialized to start the interrupt
timer and the interval is measured by the Z80. A single interrupt takes approximately 2.048ms.
E6 Lexichip II WCS Test
The WCS test is the similar to the SRAM test with the exception that the entire memory testing is
destructive. A counter test and a data write and read test is performed.
The counter test writes a 0 into the first location, a 1 into the next, then a 2, etc. This repeats this until the
entire section of the WCS memory is tested.
The data write and read test, writes and reads the memory with 55h, AAh, FFh, 00h, 01h, 02h, 04h, 08h,
10h, 20h, 40h, 80h, FEh, FDh, FBh, F7h, EFh, DFh, BFh, and 7Fh. The last 16 patterns shift 1's and 0's
through the memory locations.
E7 Lexichip II DRAM Test
This test uses a counter test and a single data write and read test. A single data write and read test is used
during the power on diagnostics to conserve time. The Extended Diagnostics use additional data patterns
due to more time being allotted to perform these tests.
The counter test writes a 0 into the first location, a 1 into the next, then a 2, etc. This repeats this until the
entire section of the WCS memory is tested. The data test writes and reads the memory with 55555h.
E8 56004 SPI Test
This test verifies the 56004 is verified to be able to boot and to pass data. The test does not fully verify the
audio processing function of the 56004. However, if the 56004 can pass this test, which also exercises the
CPU of the 56004, most of the internal workings of the chip are operational. First the 56004 is reset and test
program is loaded. If the 56004’s internal ROM comes out of reset, it has booted and completed its internal
boot program. This indicates that a fair amount of its internal circuitry is working. Then test data patterns are
sent via the serial host interface and read back via the SC_RETURN_DATA line. If the data returned
matches what was sent, the test passes.
If the test fails the 56004 can be isolated from the path in the Extended Diagnostic. See section LOOP SPI
Test for information on how to remove the 56004 from the data path, thus isolating the failure to the 56004
or to the communication circuitry.