Chapter 8: ENC/ENS/ENX-6801/M Encoder Modules and Accessories
Block Diagram
114
6800/7000 Series - Audio and Video Multi/Demultiplexing Products Installation and Operation Manual
Block Diagram
Figure 8-2.
ENC/ENS/ENX-6801 Block Diagram
Deserializer and FIFO Delay
The serial digital video enters the module through a 75 W terminating
BNC connector. The serial reclocking input stage removes high
frequency jitter and also auto-equalizes cable losses (up to 300 m of
cable) in case of a 270MHz 4:2:2 serial signal. The remaining low-
frequency portion of the jitter is removed by the 27 MHz parallel clock
PLL loop that supplies the read clock for the U20 FIFO chip. The
function of the 5K word length FIFO is to adjust the module's delay
between the minimum latency and a maximum 2.9 horizontal line delay.
The on-board FIFO can be switched to
Line-store
mode up to one full
line, and in this case, the reference has to be within one line range. The
module's functionality can be expanded by adding the 6801FS-IO frame
synchronizer sub-board to the A1 connector.