MIPI DSI to OpenLDI/FPD-Link/LVDS Interface Bridge Soft IP
User Guide
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FPGA-IPUG-02003-1.2
Table 2.2. Capture Controller Outputs
(Continued)
Port Name
Direction
Function description
lp2_en_o
Output
Long packet enable. Goes high for 1 byte clock cycle when long packet is detected from the
higher byte when RX_GEAR=16 (active high)
lp_av_en_o
Output
Long packet enable for active video data. Goes high for 1 byte clock cycle when long
packet containing active video is detected (active high)
lp2_av_en_o
Output
Long packet enable for active video data. Goes high for 1 byte clock cycle when long
packet containing active video is detected from the higher byte when RX_GEAR=16 (active
high)
vc_o[1:0]
Output
Virtual channel
vc2_o[1:0]
Output
Virtual channel from higher byte when RX_GEAR=16
wc_o[15:0]
Output
Word count of long packet
wc2_o[15:0]
Output
Word count of long packet from higher byte when RX_GEAR=16
dt_o[5:0]
Output
Data type
dt2_o[5:0]
Output
Data type from higher byte when RX_GEAR=16
ecc_o[7:0]
Output
ECC of packet header
ecc2_o[7:0]
Output
ECC of packet header from higher byte when RX_GEAR=16
2.5.
Byte2Pixel
When two Rx channels are enabled, each channel has its own byte2pixel. This block converts byte data into pixel data
using FIFO. Continuous byte clock is used to write data to FIFO while pixel clock is used to read data from FIFO.
The VSYNC and HSYNC outputs are also generated by this block and transferred to pixel clock domain using
synchronization registers. Since only DSI Non-Burst Mode with Sync Pulses is supported, the generation of VSYNC and
HSYNC control signals is dependent on the MIPI DSI host device as follows. VSYNC goes active high and inactive low
when the “VSYNC Start” and “VSYNC End” short packets are seen, respectively. HSYNC goes active high when the
“HSYNC Start”, “VSYNC Start” and “VSYNC End” short packets are seen. HSYNC goes inactive low when the “HSYNC
end” short packet is seen. MIPI DSI Non-Burst Mode with Sync Events and Burst Mode operations are not supported.
2.6.
Lane Distribution
When two Rx channels are enabled, each channel has its own lane distribution. This block is the interface between
byte2pixel and lvds wrapper. It rearranges pixel data bits according to OpenLDI unbalanced format discussed in the
section on page 6. The arranged data bits are fed to lvds wrapper for transmission over LVDS lanes.
When TX_GEAR=14 and/or two Tx channels are enabled, multiple pixels are received from byte2pixel in one pixel clock
cycle. There may be cases when not all of the pixels received in one cycle are valid, for example odd number of pixels.
This module uses p_odd_o output of byte2pixel to determine which of the pixels are valid.
2.7.
LVDS Wrapper
This block instantiates one ODDRx7 or one ODDRx14 primitive to serialize parallel data for each LVDS data lane.
Selection between ODDRx7 and ODDRx14 depends on Tx gear setting. The clock lane is generated by feeding constant
“1100011” or “11000111100011” to another ODDRx7 or ODDRx14, respectively.
This block also divides PLL output clock to generate pixel clock.
A reset synchronization module is enclosed within this block. It takes care of the reset sequence of ODDR blocks and
other DDR primitives. Start of HS transmission should only begin when reset synchronization sequence is complete.
This block drives its output ready_o high when reset synchronization sequence is complete.