Lattice Semiconductor MachXO2 Breakout Board User Manual Download Page 27

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MachXO2 Breakout Board Evaluation Kit

Evaluation Board User Guide

Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at

www.latticesemi.com/legal

All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

FPGA-EB-02051-2.3

Figure A.3. FPGA

MAKE PWR TRACES
CAPABLE OF 1A

PR10D

PR10C

PR10B

PR10A

PR9D

PR9C

PR9B

PR9A

PR8D

PR8C

PR8B

PR8A

PCLKC1_PR5D

PR5B

PCLKT1_PR5C

PR5A

PR4D

PR4B

PR4C

PR4A

PT17D_DONE

PT17C_INITn

PT17B

PT17A

PT16D

PT16C

PT15D_PROGn

PT15C_JTAGen

PT15B

PT15A

PT12D_SDA_PCLKC0_0

PT12B_PCLKC0_1

PT12C_SCL_PCLT0_0

PT12A_PCLKT0_1

PT11D_TMS

PT11B

PT11C_TCK_TESTCLK

PT11A

PT10D_TDI

PT10C_TDO

PT10B

PT10A

PT9D

PT9C

PT9B

PT9A

PR10D

PR10B

PR10C

PR10A

PR9D

PR9B

PR9C

PR9A

PR8D

PR8B

PR8C

PR8A

PCLKC1_PR5D

PR5B

PCLKT1_PR5C

PR5A

PR4D

PR4C

PR4B

PR4A

PR3B

PR2D

PR2B

PR3A

PR2C

PR2A

PT16B

PT16A

PR2B

PR2A

PR2D

PR2C

PR3B

PR3A

PT17B

PT17A

PT16B

PT16A

PT15A

PT15B

PT12B_PCLKC0_1

PT12A_PCLKT0_1

PT11B

PT11A

PT10B

PT10A

PT9B

PT9A

PT12C_SCL_PCLT0_0

PT12D_SDA_PCLKC0_0

PT17C_INITn

PT17D_DONE

PT16C

PT15D_PROGn

PT15C_JTAGen

PT11D_TMS

PT11C_TCK_TESTCLK

PT9D

PT9C

PT10D_TDI

PT10C_TDO

PT16D

VCCIO0

VCCIO1

VCC_1.2V

VCCIO0

VCCIO1

+3.3V

VCCIO0

+3.3V

VCCIO1

+3.3V

TDO

TDI

TMS

TCK

LED0

LED1

LED2

LED3

LED4

LED5

LED6

LED7

RS232_Rx_TTL

RS232_Tx_TTL

RTSn

DTRn

CTSn

DSRn

DCDn

TTTitttllleee

SSSizzzeee

Document Number

Dattteee:::

SSShhheeeeeettt

ooof

LLLCMXX

MXO

O222---111200ZEE

200Z

200ZE---BBB---EEEVVVN

AXELSY

AXELSYS

Lattice MachXO2 1200ZE Breakout Board - FPGA

BBB

333

555

Header2x20

DNI

C23

0.1uF

C15

0.1uF

C21

0.01uF

Header2x20

DNI

C18

0.1uF

C20

0.1uF

BANK 0

BANK 1

LCMXO2-1200ZE-1TG144C

U3-2

PT17D/DONE

109

PT17C/INITn

110

PT17B

111

PT17A

112

PT16D

113

PT16C

114

PT16B

115

PT16A

117

VCCIO0

118

PT15D/PROGRAMn

119

PT15C/JTAGENB

120

PT15B

121

PT15A

122

VCCIO0

123

VCCIO0

135

PT12D/SDA/PCLKC0_0

125

PT12C/SCL/PCLKT0_0

126

PT12B/PCLKC0_1

127

PT12A/PCLKT0_1

128

PT11D/TMS

130

PT11C/TCK/TEST_CLK

131

PT11B

132

PT11A

133

PT10D/TDI

136

PT10C/TDO

137

PT10B

138

PT10A

139

PT9D

140

PT9C

141

PT9B

142

PT9A

143

PR10D

PR10C

PR10B

PR10A

VCCIO1

102

PR9D

PR9C

PR9B

PR9A

PR8D

PR8C

PR8B

PR8A

NC4

NC5

PCLKC1_0/PR5D

PCLKT1_0/PR5C

PR5B

PR5A

PR4D

PR4C

PR4B

PR4A

PR3B

PR3A

100

NC6

103

PR2D

104

PR2C

105

PR2B

106

PR2A

107

C22

0.1uF

R24

R23

2k2

C17

0.01uF

C19

0.1uF

R22

2k2

R25

C24

0.1uF

Thursday, April 21, 2011

Note:

1. The Pin Functions indicated in the schematic symbol U3 are for LCMXO2-1200ZE-1TG144C. For the Pin Functions of the board with

LCMXO2-7000HE-4TG144C, refer to the pinout file.

Summary of Contents for MachXO2 Breakout Board

Page 1: ...MachXO2 Breakout Board Evaluation Kit Evaluation Board User Guide FPGA EB 02051 2 3 February 2022 ...

Page 2: ...vided AS IS with all faults and associated risk the responsibility entirely of the Buyer Buyer shall not rely on any data and performance specifications or parameters provided herein Products sold by Lattice have been subject to limited testing and it is the Buyer s responsibility to independently determine the suitability of any products and to test and verify the same No Lattice products should ...

Page 3: ...h the Lattice Diamond Programmer 11 7 MachXO2 Breakout Board 12 7 1 Overview 12 7 2 Subsystems 13 7 2 1 Clock Sources 13 7 2 2 Expansion Header Landings 13 7 2 3 MachXO2 FPGA 19 7 2 4 JTAG Interface Circuits 19 7 2 5 Power Supply 20 7 2 6 Test Points 20 7 2 7 USB Programming and Debug Interface 20 7 3 Board Modifications 21 7 3 1 Bypassing the USB Programming Interface 21 7 3 2 Applying External P...

Page 4: ... J4 Header Landing Callout 18 Figure 7 3 J3 J5 Header Landing Callout 18 Figure 7 4 J1 Header Landing and LED Array Callout 19 Figure A 1 Block Diagram 25 Figure A 2 USB Interface to JTAG 26 Figure A 3 FPGA 27 Figure A 4 FPGA 28 Figure A 5 Power LEDs 29 Tables Table 7 1 Breakout Board Components and Interfaces 13 Table 7 2 Expansion Connector Reference 13 Table 7 3 Expansion Header Pin Information...

Page 5: ...emarks of their respective holders The specifications and information herein are subject to change without notice FPGA EB 02051 2 3 5 Acronyms in This Document A list of acronyms used in this document Acronym Definition DIP Dual In line Package FPGA Field Programmable Gate Array LED Light Emitting Diode LUT Look Up Table NVCM Non Volatile Configuration Memory PCB Printed Circuit Board RoHS Restric...

Page 6: ...atic electricity can severely shorten the lifespan of electronic components See the Storage Handling section of this document for handling and storage tips 2 Features The MachXO2 Breakout Board Evaluation Kit includes MachXO2Breakout Board The board is a 3 inches x 3 inches form factor that features the following on board components and circuits MachXO2 FPGA Current board version LCMXO2 7000HE 4TG...

Page 7: ...re trademarks or registered trademarks of their respective holders The specifications and information herein are subject to change without notice FPGA EB 02051 2 3 7 Two 2 20 Header Landings J3 J5 Two 2 20 Header Landings J2 J4 MachXO2 PLD U3 FTDI USB to UART FIFOIC U1 JTAG Header Landing J1 USB Mini B Socket J7 Power LED PWR_ON Power GNDTest Points TP1 TP2 TP3 4 15 60 Hole Prototype Array J6 LED ...

Page 8: ...rements You should install the following software before you begin developing designs for the Breakout Board Lattice Diamond design software FTDI Chip USB hardware drivers installed as an option within the Diamond installation program 5 MachXO2 Device This board currently features the MachXO2 7000HE FPGA which offers embedded Flash technology for instant on non volatile operation in a single chip ...

Page 9: ...k Generator 2 08 MHz c_delay 21 0 c_delay 20 2 Hz Figure 6 1 Demonstration Design Block Diagram WARNING Do not connect the Breakout Board to your PC before you follow the driver installation procedure of this section Communication with the Breakout Board with a PC via the USB connection cable requires installation of the FTDI chip USB hardware drivers Loading these drivers enables the computer to ...

Page 10: ...he demonstration design automatically loads and drive the LED array in a repeating pattern See the Troubleshooting section of this guide if the board does not function as expected 6 2 Download Demo Designs The counter demo is preprogrammed into the Breakout Board however over time it is likely your board will be modified Lattice distributes source and programming files for demonstration designs co...

Page 11: ...pre programmed into the MachXO2 MachXO3 board by Lattice If you have changed the design but now want to restore the board to factory settings use the procedure described below To program the MachXO2 device 1 Install license and run Lattice Diamond software See http www latticesemi com latticediamond for download and licensing information 2 Connect the USB cable to the host PC and the MachXO3 board...

Page 12: ...lopment platform for the MachXO2 FPGA The board includes a proto typing area a USB program power port an LED array and header landings with electrical connections to most of the FPGA s programmable I O power and JTAG pins The board is powered by the PC s USB port or optionally with external power You may create or modify the program files and reprogram the board using Lattice Diamond software Mach...

Page 13: ...pin TQFP Interfaces LED Array Output D8 D1 Red LEDs Four 2 20 Header Landings I O J2 header_2x20 J3 header_2x20 J4 header_2x20 J5 header_2x20 User definable I O 1 8 Header Landing I O J1 header_1x8 Optional JTAG interface 4 15 60 Hole Prototype Area Prototype area 100mil centered holes Test Points Power TP1 3 3 V TP2 1 2 V TP3 GND Power and ground reference points 7 2 Subsystems This section descr...

Page 14: ...D DONE 109 4 PT17C INITn PT36C INITn 110 5 PT17B PT36B 111 6 PT17A PT36A 112 7 GND GND 8 GND GND 9 PT16D PT33B 113 10 PT16C PT33A 114 11 PT16B PT28B 115 12 PT16A PT28A 117 13 PT15D PROGn PT27D PROGn 119 14 PT15C JTAGen PT27C JTAGen 120 15 GND GND 16 GND GND 17 PT15B PT25B 121 18 PT15A PT25A 122 19 PT12D SDA PCLKC0_0 PT22D SDA PCLKC0_0 125 20 PT12C SCL PCLKT0_0 PT22C SCL PCLKT0_0 126 21 PT12B PCLKC...

Page 15: ...Function MachXO2 Pin 1 VCC_1 2V VCC_1 2V 36 72 108 144 2 VCCIO1 VCCIO1 79 88 102 3 VCC_1 2V VCC_1 2V 36 72 108 144 4 NC NC 5 PR10C PR24A 74 6 PR10D PR24B 73 7 PR10A PR23A 76 8 PR10B PR23B 75 9 GND GND 10 GND GND 11 PR9C PR21A 78 12 PR9D PR21B 77 13 PR9A PR18A 82 14 PR9B PR18B 81 15 GND GND 16 GND GND 17 PR8C PR17A 84 18 PR8D PR17B 83 19 PR8A PR16A 86 20 PR8B PR16B 85 21 GND GND 22 GND GND 23 PR5C ...

Page 16: ...16 VCCIO4 7 VCCIO5 3 VCC_3 3V VCC_3 3V 4 NC NC 5 PL2A L_GPLLT_FB PL3A L_GPLLT_FB 1 6 PL2B L_GPPLC_FB PL3B L_GPPLC_FB 2 7 PL2C L_GPLLT_IN PL4A L_GPLLT_IN 3 8 PL2D L_GPLLC_IN PL4B L_GPLLC_IN 4 9 PL3A PCLKT3_2 PL6A PCLKT5_0 5 10 PL3B PCLKC3_2 PL6B PCLKC5_0 6 11 PL3C PL8A 9 12 PL3D PL8B 10 13 GND GND 14 GND GND 15 PL4A PL9A 11 16 PL4B PL9B 12 17 PL4C PL10A 13 18 PL4D PL10B 14 19 GND GND 20 GND GND 21 ...

Page 17: ...51 66 3 PB20D SI SISPI PB38B SI SISPI 71 4 PB20B PB37B 69 5 PB20C SN PB38A SN 70 6 PB20A PB37A 68 7 PB18D PB35B 67 8 PB18B PB31B 62 9 PB18C PB35A 65 10 PB18A PB31A 61 11 GND GND 12 GND GND 13 PB15D PB29B 60 14 PB15B PB26B 58 15 PB15C PB29A 59 16 PB15A PB26A 57 17 GND GND 18 GND GND 19 PB11B PCLKC2_1 PB23B PCLKC2_1 56 20 PB11D PB18B 54 21 PB11A PCLKT2_1 PB23A PCLKT2_1 55 22 PB11C PB18A 52 23 GND GN...

Page 18: ...ND 121 122 125 126 127 128 GND GND 130 131 132 133 136 137 GND GND 138 139 140 141 142 143 GND GND 1 2 J2 3 3 IO3 3 3 NC 1 2 3 4 5 6 9 10 GND GND 11 12 13 14 GND GND 19 20 21 22 GND GND 23 24 25 26 GND GND 27 28 GND GND 32 33 34 35 1 2 J4 Top Side J2 J4 LCM XO2 7000 HE4TG144C Figure 7 2 J3 J4 Header Landing Callout LCM XO 2 7000 HE4TG144C 1 2 IO1 1 2 NC 74 73 76 75 GND GND 78 77 82 81 GND GND 84 8...

Page 19: ...PGA The MachXO2 7000HE 4TG144C is a 144 pin TQFP package FPGA device which provides up to 114 usable I O in a 20 mm 20 mm package 108 I O are accessible from the breakout board headers Table 7 6 MachXO2 and MachXO3 FPGA Interface Reference Item Description Reference Designators U3 Part Number LCMXO2 7000HE 4TG144C Manufacturer Lattice Semiconductor Web Site www latticesemi com 7 2 4 JTAG Interface...

Page 20: ...ed LEDs D1 D2 D3 D4 D5 D6 D7 D8 Green LEDs D9 Part Number LTST C190KRKT D1 D8 LTST C190KGKT D9 Manufacturer Lite On It Corporation Web Site www liteonit com 7 2 5 Power Supply 3 3 V and 1 2 V power supply rails are converted from the USB 5 V interface when the board is connected to a host PC 7 2 6 Test Points In order to check the various voltage levels used the following test points are provided ...

Page 21: ...emoving the 0 Ω resistors R42 VCC_1 2 V and R44 VCC_3 3 V Power connections are available from the expansion header landings J3 1 2 V pins 1 and 3 schematic sheet 3 of 5 and J4 3 3 V pins 1 and 3 schematic sheet 4 of 5 7 3 3 Measuring Bank and Core Power In addition to the expansion headers test points TP1 TP2 provide access to power supplies of the MachXO2 FPGA Inline 1 ohm resistors R24 VCCIO0 3...

Page 22: ...ect USB driver may have been installed This usually occurs if you attach the board to your PC prior to installing the Lattice supplied USB driver 8 3 To access the Troubleshooting the USB Driver Installation Guide To access the installation guide for Diamond software and standalone Diamond Programmer 1 Start Diamond or Diamond Programmer and choose Help 2 Search for USB driver or Troubleshooting t...

Page 23: ...trademarks of their respective holders The specifications and information herein are subject to change without notice FPGA EB 02051 2 3 23 9 Ordering Information Table 9 1 Ordering Information Description Ordering Part Number China RoHS Environment Friendly Use Period EFUP MachXO2 7000HE Breakout Board Evaluation Kit LCMXO2 7000HE B EVN MachXO2 Breakout Board Evaluation Kit LCMXO2 1200ZE B EVN Not...

Page 24: ...nd disclaimers are as listed at www latticesemi com legal All other brand or product names are trademarks or registered trademarks of their respective holders The specifications and information herein are subject to change without notice 24 FPGA EB 02051 2 3 Technical Support Assistance Submit a technical support case through www latticesemi com techsupport ...

Page 25: ... device Please consult Tables 3 through 6 for 1200 and 7000HE pin name and bank synonyms Pin numbers are correct for either device Figure A 1 Block Diagram 5 5 4 4 3 3 2 2 1 1 D C B A Power from USB 5V BANK 3 BANK 1 BANK 0 FPGA LCMXO2 7000HE 4TG144C or LCMXO2 1200ZE 1TG144C BANK 2 HEADER HEADER HEADER I Os SPI I Os I Os HEADER I Os I2C JTAG RS232 USB CONNECTOR USB to JTAG RS232 LEDS 1 8 i i T T Ti...

Page 26: ...d USB to JTAG B B B 2 2 2 5 5 5 0 DNI R17 L1 600ohm 500mA 1 2 R13 10k C14 18pF R3 5k1 0 DNI R18 R9 2k2 C8 0 1uF C10 10uF R7 0 0 DNI R14 R19 2k2 0 DNI R20 FTDI High Speed USB FT2232H FT2232HL U1 VREGIN 50 VREGOUT 49 DM 7 DP 8 REF 6 RESET 14 EECS 63 EECLK 62 EEDATA 61 OSCI 2 OSCO 3 TEST 13 ADBUS0 16 ADBUS1 17 ADBUS2 18 ADBUS3 19 VPHY 4 VPLL 9 VCORE 12 VCORE 37 VCORE 64 VCCIO 20 VCCIO 31 VCCIO 42 VCC...

Page 27: ... RS232_Rx_TTL 2 RS232_Tx_TTL 2 RTSn 2 DTRn 2 CTSn 2 DSRn 2 DCDn 2 i i T T Tit t tl l le e e i i S S Siz z ze e e Document Number a a D D Dat t te e e S S Sh h he e ee e et t t f f o o of C C L L LCMX X M MXO O O2 2 2 1 1 1200ZE E 200Z 200ZE B B B E E EV V VN N N S S AXELSY AXELSY AXELSYS Lattice MachXO2 1200ZE Breakout Board FPGA B B B 3 3 3 5 5 5 J2 Header2x20 DNI 2 4 6 8 10 12 14 16 18 20 24 22 ...

Page 28: ... i i S S Siz z ze e e Document Number a a D D Dat t te e e S S Sh h he e ee e et t t f f o o of S S AXELSY AXELSY AXELSYS C C L L LCMX X M MXO O O2 2 2 1 1 1200ZE E 200Z 200ZE B B B E E EV V VN N N B B B 4 4 4 5 5 5 100 R31 DNI 100 R35 DNI C53 0 1uF 100 R41 DNI 100 R38 DNI 100 R32 DNI R37 DNI J5 Header2x20 DNI 2 4 6 8 10 12 14 16 18 20 24 22 26 28 30 32 34 36 38 40 39 37 35 33 31 29 27 25 23 21 19...

Page 29: ... e et t t f f o o of C C L L LCMX X M MXO O O2 2 2 1 1 1200ZE E 200Z 200ZE B B B E E EV V VN N N S S AXELSY AXELSY AXELSYS i i T T Tit t tl l le e e Lattice MachXO2 1200ZE Breakout Board Power LEDs B B B 5 5 5 5 5 5 D3 Red 1 2 R47 1K C39 0 1uF J6 Proto Type Area Holes on 0 1 inch Centers Proto Type Area 1 D5 Red 1 2 R42 0 TP2 DNI 1 C44 0 1uF C48 10uF LCMXO2 1200ZE 1TG144C U3 1 VCC 36 VCC 72 VCCP 1...

Page 30: ... C32 C33 C34 C37 C38 C39 C40 C44 C50 C51 C52 C53 Kemet 2 34 3 5 C10 C35 C42 C46 C48 Taiyo Yuden 3 5 4 2 C13 C14 Kemet 4 2 5 6 C17 C21 C27 C31 C41 C45 Kemet 5 6 6 2 C36 C43 Kemet 6 2 7 2 C47 C49 Taiyo Yuden 7 2 8 8 D1 D2 D3 D4 D5 D6 D7 D8 LITE On Inc 8 8 9 1 D9 LITE On Inc 9 1 10 1 J1 Molex 10 1 11 4 J2 J3 J4 J5 Samtec 11 4 12 1 J6 12 1 13 1 J7 Neltron 13 1 14 5 L1 L2 L3 L4 L5 Murata 14 5 15 3 R1 R...

Page 31: ... www latticesemi com legal All other brand or product names are trademarks or registered trademarks of their respective holders The specifications and information herein are subject to change without notice FPGA EB 02051 2 3 31 Item Quantity Reference Value Manufacturer MFG Pin 29 1 U4 Fairchild Semi 29 1 30 1 U5 On Semi 30 1 31 1 X1 TXC 7M 12 000MAAJ T 31 32 1 X2 CTS CB3LV 3C 50M0000 32 ...

Page 32: ...footnote 1 2 3 and 4 and removed LCMXO2 7000HE 4TG144C from Figure A 4 FPGA Revision 2 2 January 2014 Section Change Summary All Updated description and procedure for downloading demo designs in Download Demo Designs section Updated project file name in Programming a Demo Design with the Lattice Diamond Programmer section Revision 2 1 September 2013 Section Change Summary All Updated procedure in ...

Page 33: ...www latticesemi com ...

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