Lattice Semiconductor MachXO2 Breakout Board, User Manual

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MachXO2 Breakout Board Evaluation Kit
Evaluation Board User Guide
© 2014-202
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Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal .
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02051-2.3 17
Expansion Header Pin Information (J5)
Header Pin Number -1200ZE Function -7000HE Function MachXO2 Pin
1 NC NC —
2 VCCIO2 VCCIO2 37, 51, 66
3 PB20D / SI / SISPI PB38B / SI / SISPI 71
4 PB20B PB37B 69
5 PB20C / SN PB38A / SN 70
6 PB20A PB37A 68
7 PB18D PB35B 67
8 PB18B PB31B 62
9 PB18C PB35A 65
10 PB18A PB31A 61
11 GND GND —
12 GND GND —
13 PB15D PB29B 60
14 PB15B PB26B 58
15 PB15C PB29A 59
16 PB15A PB26A 57
17 GND GND —
18 GND GND —
19 PB11B / PCLKC2_1 PB23B / PCLKC2_1 56
20 PB11D PB18B 54
21 PB11A / PCLKT2_1 PB23A / PCLKT2_1 55
22 PB11C PB18A 52
23 GND GND —
24 GND GND —
25 PB9B / PCLKC2_0 PB16B / PCLKC2_0 50
26 PB9D PB13B 48
27 PB9A / PCLKT2_0 PB16A / PCLKT2_0 49
28 PB9C PB13A 47
29 GND GND —
30 GND GND —
31 PB6D / S0 / SPISO PB12B / S0 / SPISO 45
32 PB6B PB9B 43
33 PB6C / MCLK / CCLK PB12A / MCLK / CCLK 44
34 PB6A PB9A 42
35 GND GND —
36 GND GND —
37 PB4D PB6B 41
38 PB4B PB4B 39
39 PB4C / CSSPIN PB6A / CSSPIN 40
40 PB4A PB4A 38