3
LatticeSC PCI Express x1
Lattice Semiconductor
Evaluation Board User’s Guide
• RS-232 Communications Port
• Logic analyzer connection
• Liquid Crystal Display interface connection
• User-defined input and output points
• SMA connectors included for high-speed clock or data interfacing
• Performance monitoring via test headers, LEDs and switches
The contents of this user’s guide include top-level functional descriptions of the various portions of the evaluation
board, descriptions of the on-board connectors, diodes and switches and a complete set of schematics of the
board. Figure 2 shows the functional partitioning of the board.
Figure 2. LatticeSC PCI Express x1 Evaluation Board Block Diagram
Additional Resources
For additional information and resources related to this board, including updated documentation and software
demos, please see the Lattice web site at: www.latticesemi.com/boards, and navigate to the appropriate page for
this board.
Lattice makes its best effort to provide evaluation board designs to help users with evaluation and development.
However it remains the user's responsibility to verify proper and reliable operation of Lattice products in their end
application by consulting documentation provided by Lattice. Differences in component selection and/or PCB layout
in the user's application may significantly affect circuit performance and reliability.
SC15/SC25
900 fpBGA
FlxMac
RIGHT
LEFT
FlxMac
BOTTOM
X1 PCIe
Fingers
1G
b
e-SFP
National
PHY
RJ-45
RS-232
2x5 COM
10/100/1000
QDR2
Flash
Osc
SGMII
SATA-Host
JTAG
Orcastra
ma
gn
etic
s
Power Regulation
12
V
Edge Fingers
12
V
WallWart
Terminal Block
x1 PCI Express Dri
v
er
Platform Board
for LatticSC
900 fpBGA De
v
ices
Config
Status & Control
Backpanel Slot
Backpanel Slot
PCI Clk
PLL
*1.25
SATA-Target
Testpoints
LEDs
Switches
Osc
Clock Control
I2C
EE
PROM
Maxim
6692
PTEMP
SERDES
Loop
SERDES
SMAs
Osc
REFCLK-RIGHT
REFCLK-LEFT
100MHz
Differential
Trace
Loops
RLDRAM2
L
V
DS
SMAs
18-
b
it
18-
b
it
