Lattice Semiconductor ECP5-5G, User Manual

Page: 24 / 32

24
ECP5-5G Versa Development Board
Figure 19. DDR3 Memory
5 5
4 4
3 3
2 2
1 1
D
D
C
C
B
B
A
A
ALL Memory controller buses, clocks, and control traces must be 50 Ohm Transmission lines
PLACE CLOSE TO MEMORY CHIP
Place Address/Control Termination Resistors as close as possible to Memory Chip U7
VTT
X1 needs to be matched length for all traces
U1 Pin
MEMORY DEVICE TERMINATION for ADDRESS/ CONTROL SIGNALS
X1
X2
Termination at end of line
Memory
Place close to FPGA
Schematic symbols rev 4.1
Schematic symbols rev 4.1
Bank 6
Bank 7
DDR3_A3
DDR3_D
Q
1
DDR3_D
Q
4
DDR3_D
Q
2
DDR3_D
Q
0
DDR3_D
Q
5
DDR3_D
Q
7
DDR3_D
Q
3
DDR3_DM1
DDR3_
V
RE
F
DDR3_A5 DDR3_A3 DDR3_A0 DDR3_A
8
DDR3_A4 DDR3_A1 DDR3_A7 DDR3_A6 DDR3_A2 DDR3_A9 DDR3_A10
DDR3_ K0
DD R3_K 0#
DDR3_A12 DDR3_A11
DDR3_BA2 DDR3_A12 DDR3_BA1 DDR3_RAS# DDR3_A
8
DDR3_A
5
DDR3_A
2
DDR3_A11
DDR3_SD0
DDR3_CS0# DDR3_D
Q
9
DDR3_D
Q
1
2
DDR3_D
Q
1
4
DDR3_D
Q
1
0
DDR3_D
Q
8
DDR3_D
Q
1
3
DDR3_D
Q
1
5
DDR3_D
Q
1
1
DDR3_ V S
DDR3_O
DT0
DDR3_RAS# DDR3_
W
E#
DDR3_CE0 DDR3_K0# DDR3_BA0 DDR3_BA1 DDR3_RST
#
KOC
DDR3_A4 DDR3_A0 DDR3_A10 DDR3_CAS# DDR3_A9 DDR3_A1 DDR3_A6
DDR3_D
Q
S
0
#
DDR3_D
Q
S
1
#
DDR3_D
Q
S
1
DDR3_D
Q
S
0
DDR3_A7
DDR3_BA2
DDR3_O
DT0
DDR3_D
Q
6
ZQ
0
MEM_
V
REF
DDR3_DM0 DDR3_CAS# DDR3_K0
DDR3_BA0
DDR3_
W
E#
DDR3_CE0 DDR3_CS0#
DDR3_A
0
DDR3_A
2
DDR3_ V REF
MEM_
V
REF
ECP5_
V
RE
F
DDR3_A
6
DDR3_A
9
DDR3_A
3
DDR3_A
1
DDR3_A11 DDR3_A
4
DDR3_A
7
DDR3_A10 DDR3_A12 DDR3_A
5
DDR3_BA0 DDR3_BA1 DDR3_BA2 DDR3_CAS
#
DDR3_CE0 DDR3_O
D
T
0
DDR3_
W
E#
DDR3_RAS
#
DDR3_D
Q
3
DDR3_D
Q
1
DDR3_D
Q
0
DDR3_D
Q
4
DDR3_D
Q
2
DDR3_D
Q
5
DDR3_D
Q
7
DDR3_D
Q
1
1
DDR3_D
Q
1
5
DDR3_D
Q
1
0
DDR3_D
Q
1
2
DDR3_DM1 DDR3_D
Q
1
4
DDR3_D
Q
8
DDR3_D
Q
9
DDR3_D
Q
1
3
DDR3_D
Q
S
0#
DDR3_D
Q
S
0
DDR3_RST
#
PCLKT0 PCLKC0
S
W
IT
CH4
S
W
IT
CH3
S
W
IT
CH2
S
W
IT
CH1
S W ITCH[1.. 8 ]
S
W
IT
CH4
S
W
IT
CH3
S
W
IT
CH2
S
W
IT
CH1
100M
H
z
100M
H
z
_
N
DDR3_K0# DDR3_K
0
100M
H
z
100M
H
z
_
N
ECP5_
V
RE
F
DDR3_DM0
DDR3_D
Q
S
1#
DDR3_D
Q
S
1
DDR3_A
8
100M
H
z
_
N
100M
H
z
ECP5_
V
RE
F
DDR3_D
Q
6
DDR3_CS0
#
1_5
V
1_5
V
2_5
V
2_5
V
DDR3_
V
TT
DDR3_
V
TT
DDR3_
V
DD
1_5
V
DDR3_
V
DDQ
DDR3_
V
DD
DDR3_
V
DDQ
1_5
V
DDR3_
V
TT
1_5
V
1_5
V
1_5
V
1_5
V
1_5
V
3_3
V
1_5
V
1_5
V
1_5
V
1_5
V
1_5
V
1_5
V
1_5
V
1_5
V
PCLKT0
[9
]
PCLKC0
[9
]
S
W
IT
CH[
1
:
8
][
8
]
Da
te
:
Si
z
e
Sc
h
e
m
a
ti
c
Re
v
of
S
h
eet
Ti
tl
e
Lat
ti
ce
S
e
m
ic
ond
u
ct
or
Appl
ic
at
ions
E
m
a
il: te
c
h
s
u
p
p
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rt@
L
a
ttic
e
s
e
m
i.c
o
m
B
oar
d R
e
v
Pr
o
je
c
t
C
A
10
7
DDR3
Memory
ECP5
-5G
V
ERSA E
v
al
Boar
d
A
W
e
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sday
, S
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pt
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m
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r 23,
2015
Da
te
:
Si
z
e
Sc
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m
a
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c
Re
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of
S
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Ti
tl
e
Lat
ti
ce
S
e
m
ic
ond
u
ct
or
Appl
ic
at
ions
E
m
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il: te
c
h
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u
p
p
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rt@
L
a
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e
s
e
m
i.c
o
m
B
oar
d R
e
v
Pr
o
je
c
t
C
A
10
7
DDR3
Memory
ECP5
-5G
V
ERSA E
v
al
Boar
d
A
W
e
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, S
e
pt
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2015
Da
te
:
Si
z
e
Sc
h
e
m
a
ti
c
Re
v
of
S
h
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Ti
tl
e
Lat
ti
ce
S
e
m
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ond
u
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or
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at
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E
m
a
il: te
c
h
s
u
p
p
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rt@
L
a
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e
s
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m
i.c
o
m
B
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d R
e
v
Pr
o
je
c
t
C
A
10
7
DDR3
Memory
ECP5
-5G
V
ERSA E
v
al
Boar
d
A
W
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dne
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r 23,
2015
C241
10 N F-0603S MT
R1
R1
R1=50 Ohm
RP1
C
T
S
-RT1402B
7
A2
A2
B2
B2
C2
C2
D2
D2
E2
E2
F2
F2
G2
G2
H2
H2
J2
J2
A3
A3
B3
B3
C3
C3
D3
D3
E3
E3
F3
F3
G3
G3
H3
H3
J3
J3
A1
A1
B1
B1
C1
C1
D1
D1
E1
E1
F1
F1
G1
G1
H1
H1
J1
J1
R
145
0R-0603SM
T
C21 8
100 N F-0603S MT
R
150
50R-
0402S
M
T
C1 8 5
100 N F-0603S MT
LFE5UM-
4
5
F
-B
G
3
8
1
U1
F
V
CCIO7
H6
V
CCIO7
H7
V
CCIO7
J6
PL11A/ULC_GPLL0T
_
I
N
A4
PL11B/ULC_G
P
LL0C_I
N
A5
PL11C/ULC_GPLL0T
_MF
G
O
U
T
2
B5
P
L
1
1
D
/U
L
C
_
GP
L
L
0
C
_
M
F
GOUT
2
C5
PL14A/ULC_GPLL0
T
_
M
FG
O
U
T
1
C4
P
L14B/ULC_G
P
LL0C_MFG
O
U
T
1
B4
P
L14C
A3
P
L14D
B3
P
L17A
E4
P
L17B
D5
P
L17C
C3
P
L17D
D3
P
L20A
F4
P
L20B
E3
P
L20C
E5
P
L20D
F5
P
L23A
A2
P
L23B
B1
PL23C/
V
REF1_7
B2
P
L23D
C2
P
L26A
C1
P
L26B
D1
P
L26C
D2
P
L26D
E1
PL29A/G
R_PCLK7_1
H4
P
L29B
G5
P
L29C/G
R_PCLK7_0
H5
P
L29D
H3
P
L32A/PCLKT
7_1
G3
PL32B/PCLKC7_1
F3
PL32C/PCLKT
7_0
F2
PL32D/PCLKC7_0
E2
C1
7
8
1UF -16 V -0 8 05SM T
R
144
OP
E
N
-0603S
M
T
ddr
3-
96
b
ga
U
11B
DQ0
E3
DQ1
F7
DQ2
F2
DQ3
F
8
DQ4
H3
DQ5
H
8
DQ6
G2
DQ7
H7
A0
N
3
A1
P7
A2
P3
A3
N
2
A4
P
8
A5
P2
A6
R
8
A7
R2
A
8
T
8
A9
R3
A10/AP
L7
A1
1
R7
A12/BC
#
N
7
BA0
M2
BA1
N8
CAS#
K3
CK
J7
CK#
K7
CKE
K9
CS#
L2
LD
M
E7
LD
Q
S
F3
LD
Q
S
#
G3
ODT
K1
RAS#
J3
RST
#
T2
W
E#
L3
ZQ
L
8
N
C_
J
1
J1
N
C_L1
L1
N
C_
J
9
J9
N
C_L9
L9
N
C_
T
3
T3
N
C_
T
7
T7
N
C_
M
7
M7
DQ
8
D7
DQ9
C3
DQ10
C
8
DQ11
C2
DQ12
A7
DQ13
A2
DQ14
B
8
DQ15
A3
UDM
D3
UDQS
C7
UDQS#
B7
BA2
M3
R
149
OP
E
N
-0603S
M
T
C222
100 N F-0603S MT
C224
100 N F-0603S MT
C191
100 N F-0603S MT
FB21
BLM41PG
6
00S
N
1
C200
10 N F-0603S MT
PP1
1 2
C217
10 N F-0603S MT
+
C170
47UF -16 V -TA N TBSMT
R147
240R-0603S MT
C173
1UF -16 V -0 8 05SM T
C1 8 7
10 N F-0603S MT
R154
50R-
0402S
M
T
R
156
100R-
0402S
M
T
C
171
1UF -16 V -0 8 05SM T
C1 8 6
100 N F-0603S MT
R
151
50R-
0402S
M
T
R
143
OP
E
N
-0603S
M
T
LFE5UM-
4
5
F
-B
G
3
8
1
U1
E
V
CCIO6
L6
V
CCIO6
L7
V
CCIO6
M6
PL35A/PCLKT
6_1
G2
PL35B/PCLKC6_1
F1
PL35C/PCLK
T
6_0
H2
PL35D/PCLKC6_0
G1
PL3
8
A/GR_PCLK6_
0
J4
PL3
8
B
J5
PL
3
8
C/G
R
_PCLK6_1
J3
PL
3
8
D
K3
PL41A
K2
PL41B
J1
P
L41C
H1
P
L41D
K1
PL44A
K4
PL44B/
V
REF1_6
K5
P
L44C
L4
P
L44D
L5
PL53A
M5
PL59A
M4
PL59B
N
5
PL59C/D15/IO15
N
4
PL59D/D14/IO14
P5
PL62A/D13/IO1
3
N
3
PL62B/D12/IO1
2
M3
PL62C/D11/IO11
L3
PL62D/D10/IO10
L2
P
L65A/LLC_G
P
LL0T
_MF
G
O
U
T
2
N
2
PL65B/LLC_GPLL0C_
M
F
G
O
U
T
2
M1
P
L65C/D9/IO
9
L1
P
L65D/D
8
/IO
8
N
1
PL
6
8
A/LLC_G
P
LL0T
_MF
G
O
U
T
1
P1
PL6
8
B/LLC_GPLL0C_
M
F
G
O
U
T
1
P2
PL
6
8
C/LLC_G
P
LL0T
_
I
N
P3
PL6
8
D/LLC_GPLL0C_I
N
P4
C1 8 3
100 N F-0603S MT
C204
10 N F-0603S MT
C1 88
100 N F-0603S MT
U1
2
LP299
8
-S
O
8
G N D
1
SD
2
V
SE
N
SE
3
V
REF
4
V
DDQ
5
A V I N
6
P V I N
7
V
TT
8
C195
100 N F-0603S MT
C205
100 N F-0603S MT
R1
5
3
50R-
0402SM
T
C19 8
10 N F-0603S MT
R
157
10K-
0402SM
T
C
226
10
N
F-
0603S
M
T
DI
C1
8
1
1UF -16 V -0 8 05SM T
C
206
10
N
F-
0402S
M
T
C223
10 N F-0603S MT
C190
10 N F-0603S MT
C196
10 N F-0603S MT
C175
100 N F-0603S MT
C1 8 9
100 N F-0603S MT
C
225
100
N
F-
0603S
M
T
DI
FB23 MPZ
1
6
0
8
Y600B
DI
1
2
R1
4
8
OP
E
N
-0603S
M
T
+
C
179
10UF -16 V -TA N TBSMT
+
C
177
100UF -D 3PO SC AP
C1 8 2
10 N F-0603S MT
R
141
0R-
0603S
M
T
C174
100 N F-0603S MT
C
203
10
N
F-
0402S
M
T
1 2
C221
10 N F-0603S MT
X1
100_00M
H
z
_L
V
DS
Q_
N
5
Q
4
V CC
6
G N D
3
DIS#
1
N
C
2
PAD
7
C194
10 N F-0603S MT
C242
100 N F-0603S MT
FB22
BLM41PG
6
00S
N
1
ddr
3-
96
b
ga
U
11A
V
DD
B2
V
DD
D9
V
DD
K2
V
DD
K
8
V
DD
G7
V
DD
N
1
V
DD
N
9
V
DD
R1
V
DD
R9
V
DDQ
A1
V
DDQ
A
8
V
DDQ
C1
V
SS
A9
V
SS
B3
V
SS
E1
V
SS
G
8
V
SS
J2
V
SS
J
8
V
SS
M1
V
SS
M9
V
SS
P1
V
SS
P9
V
SS
T1
V
SS
T9
V
SSQ
B1
V
SSQ
B9
V
SSQ
D1
V
SSQ
D
8
V
SSQ
E
8
V
REFCA
M
8
V
DDQ
C9
V
DDQ
E9
V
DDQ
F1
V
DDQ
H9
V
REFDQ
H1
V
SSQ
F9
V
SSQ
G1
V
SSQ
G9
V
DDQ
D2
V
DDQ
H2
V
SSQ
E2
R
146
0R-0603SM
T
C192
10 N F-0603S MT
C220
100 N F-0603S MT
R142
4_7K-0603S MT
R
155
50R-
0402S
M
T
C202
10 N F-0402S MT
C1 8 4
10 N F-0603S MT
C199
100 N F-0603S MT
C219
10 N F-0603S MT
+
C
176
22UF -16 V -TA N TBSMT
+
C1
8
0
22UF -16 V -TA N TBSMT
R1
5
2
50R-
0402S
M
T
C197
100 N F-0603S MT
C201
100 N F-0603S MT
C172
100 N F-0603S MT
C193
100 N F-0603S MT