9
ECP5-5G Versa Development Board
On-Board Clock Capabilities
(See Appendix A, Sheet 9, Figure 21 - Reference Clock Generator)
The ECP5-5G Versa Development Board allows for several clock source options. Some of these options are con-
trolled via the ispClock5406D programmable clock manager device. The ispClock5406D enables the reference
clock from the PCI Express interface to provide a reference clock to the SERDES. This is true only when the board
is in a PCI Express host socket. When the board is not in a PCI Express host socket, the clock will be supplied by a
156.25 MHz clock on-board oscillator. Both clock inputs can be fanned out to the dedicated SERDES reference
inputs, FPGA inputs, and to the expansion connectors. The factory default programming provides a variety of
clocks to the SERDES and FPGA inputs to support Factory defined 5G applications. The ispClock chip may be pro-
grammed with user defined configurations to support a wide range of user applications.
Figure 9. Clock Controller Scheme
PLL
ispClock5406D (U13)
156.25MHz OSC
(X2)
100MHz PCIe CLK
(CN1)
PCIe PRSNT#
(J4)
BANK3
BANK2
BANK1
19/18
16/15
45
BANK0
48
LOCK#
MULTx2
MULTx1
REFCLK_D0
(U1:Y11/Y12)
35/34
PCLK0
(U1:A4/A5)
31/30
EXPCON_OSC
(X3:29)
27/26
REFCLK_D1
(U1:Y19/W20)
10/11
+
REFB
REFA
USER3
USER0
D30
0
1
