11
ECP5-5G Versa Development Board
FPGA Test Pins
(See Appendix A, Sheet 8, Figure 20 - LEDs and Switches)
General Purpose DIP Switches
General purpose FPGA pins are available for user applications. FPGA pins are connected to switch SW3, a SPST
slide-actuated DIP switch. The switches are connected to logic level 0 when moved to the ON position. Switch posi-
tion 1 is indicated with an arrow.
Inputs 1-4 are within a 1.5 V bank and inputs 5-8 are within a 2.5 V bank.
The user
must program inputs 1-4 to be the LVCMOS15 type and inputs 5-8 to be the LVCMOS25 type in the design.
Figure 12 shows the switches. Note the silk marking associated with SW3-7 is incorrect in revision B, SW3-7 is
mapped to K19, per Table 7.
Figure 11. ECP5-5G Versa Development Board LEDs and Switches
The designated pins are connected according to Table 7.
Table 7. FPGA Ball to DIP Switch Position
FPGA Ball Number
SW3 DIP Switch Position
H2
1
K3
2
G3
3
F2
4
J18
5
K18
6
K19
7
K20
8
