COMPONENT MAINTENANCE MANUAL
AVIATION PRODUCTS
Model FA5000
Rev. 02 Page 4
July 21/17
Description and Operation
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Figure 3. CVR Block Diagram
Figure 4 Recorder Data Flow Diagram shows the data flow diagram for the Model FA5000
CVR. The diagram shows the relationship between the hardware and the software. The
FPGA conditions all of the input data and processes it into packets. Digitized audio data
enters the FPGA and is transmitted to the processor via the TDM bus. All other data is
processed into fixed-size packets and then sent to the processor via register access. The
processor responds to the new data sent on the TDM or via the FPGA by executing inter-
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