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3.2: Introduction (L-502 concept)
for example, configuration is possible: 8-bit 2-way data bus + up to 10 data bits per input + up to 8
data bits per output. This allows the implementation of bus diagrams controlling complex digital
devices (item
).
Note the limitations of the asynchronous output for external synchronization (n.
).
The ADC, DAC, digital input and output streams are synchronized with respect to the same
f
ref
reference frequency, which can be assigned programmatically: 1.5 MHz or 2 MHz.
Hardware-based in L-502, the physical conversion frequency of the ADC and synchronous
digital input is always equal to
f
ref
, and the physical refresh rate of each DAC channel and digital
output is
f
ref
/2. Getting all the fractional frequences of the data input
f
ref
/n and
f
ref
/2m output
fractional frequencies (where m and n are natural numbers) occurs at the hardware processing level
in the FPGA and/or in the Blackfin processor.
L-502 has a mechanism of inter-module (n.
) synchronization to form a single
synchronous input-output system. Physically, the maximum possible number of L-502
synchronized modules is equal to the number of consecutive free PCI-e slots (of any size) in which
L-502 modules are to be installed and the adjacent modules are connected by synchronization
cables (the cables are not included in the main kit, they are bought separately). Programmatically,
the first L-502 module in the generated synchronization chain is assigned to the master, the others
to the slaves. Intermodular synchronization can be arranged for L-502 modules of any
modifications, including between L-502 different modifications. It is important to note that if at
least one L-502, used in the multi-module synchronization scheme, does not have a galvanic
isolation, then all other L-502s lose their galvanic isolation in this scheme (item
The L-502 has a 32-bit data word format, in which, besides the actual data for input or output,
there is also a physical channel number. This hardware binding of the physical channel number
ensures that the channel number is mistaken even if the top-level program for some reason lost an
arbitrary amount of data.
The PCI Express interface, compared to the PCI interface, has significant user benefits
associated with reliability: low-level network protocol PCI Express has a built-in error control and
correction mechanism, invisible at the program level. At the same time, the PCI Express device in
the BIOS of the computer is seen as a PCI-device, which basically allows to use the L-502 in all
operating systems, starting with DOS!
The BUS MASTER mode used in the L-502 allows you to transfer streaming data to the input
and output without the processor on the computer (the data is transferred between the RAM of the
computer and L-502 only with the resources of the bridge, the chipset of the computer), while the
L-502 module itself is a setup unit (master) of the process of data transfer. This is a cardinal
advantage with respect to
in terms of unloading the processor in the computer by
streaming data transfer operations. And for a multi-module BUS MASTER system is vital!
For advanced users: HOST DMA access mode to the internal memory of the signal processor
ADSP-BF523 allows you to apply an independent access channel to the Blackfin internal memory.
This creates a huge convenience - "transparency" with low-level Blackfin programming - to see
what happens in Blackfin memory on an independent channel. To some extent, HOST DMA can
replace JTAG. By the right convenience of the technology of the independent access channel to the
memory of the signal processor was evaluated by users even in products E-440 / E14-440 from L-
CARD!