L-Card L-502-P-G-D-I, User Manual, Page: 31 / 73

31
3.4: Operation principle and function circuit
3.4. Operation principle and function circuit
Узел
Flash-
памяти
2
МБ
HOST
DMA
ADSP-
BF523
Порты
в
/
в
PCIe
Схема
первичной
синхронизации
L-502
Схема
вторичной
синхронизации
данных АЦП
FPGA
Cyclone IV
АЦП
Комму
-
татор
ЦАП
Цифровой
в
/
в
JTAG
X1...X16, Y1...Y16, GND32
DI_SYN1, DI_SYN2
DO1...DO16
DAC1, DAC2
Подсистема
ввода-вывода
DI1...DI16
Только для
L-502- -G-
Узел гальвано
-
развязки
Только для
L-502-P- -
Только для
L-502- - -D
CONV_IN, START_IN
CONV_OUT, START_OUT
Джампер
резервной
загрузки
SDRAM
32
МБ
Fig. 3-5. Block diagram
FPGA is the basic logical element in the L-502, in which all the interface functions, the
hardware logic of ADC calibration, and the logic of the secondary synchronization are concentrated
(
3.3.5
)
Flash-memory with a capacity of 2 MB is designed to store the main and backup firmware
FPGA, calibration factors, serial number. Half the amount of Flash memory is provided for user
tasks.
The L-502 I/O subsystem includes nodes for the channel switch, ADC, DAC (L-502-
░
-
░
-D),
digital I/O, and primary synchronization circuit (
3.3.5
).
The galvanic isolation unit (L-502-
░
-G-
░) isolates all circuits of the I/O subsystem from
circuits connected electrically to any circuits of the computer.
The ADSP-BF523 signal processor (L-502-P-
░
-
░) is designed for additional data processing
and control. If the processor is enabled, the entire data stream and the I/O subsystem are transferred
through the processor's I/O ports. For example, it is possible to create a control loop through a
ADC secondary
synchronization
data scheme
Galvanic isolation
node
I/O
sub-system
L-502 primary
synchronization
scheme
Only for
Only for
Only for
ADC
DAC
Digital
O/I
Backup data
jumper
Switch
2MB
Flash
Memory
Node
O/I ports
32 MB