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PC/104 VGALCD-6 document name:< PC104 VGALCD-6-M12 >
Pin Discription
JIPA Interface Pin Description
You can connect various flat-display panels to the 72-pin JIPA display
connector X5. The pinout is shown in the following table.
Pin Name
Pin Description
FLM
LCD Frame Start: This output provides a
pulse to start a new frame on flat panels.
LP
LCD Line Clock: This output drives the LCD
panel-line clock. Some panel manufacturers
also designate this signal as LP or CP1.
FPVCC
Part of panel-power sequencing. This pin is
a switch output pin and used to drive the
PanelVCC
Switch on the Jipa Adapter.
FPBACK
Part of panel-power sequencing. This pin is
a switch output pin and used to drive the
Backlight VCCSwitch on the Jipa Adapter.
FPVEE
Part of panel-power sequencing. This pin is
a switch output pin and used to drive the
Contrast VEESwitch on the Jipa Adapter.
PD0-PD23
Panel Data Signals
SCLK
Flat Panel Video Clock: This signal drives the
shift clock of the flat panel, which is
designated as CP2 by some panel
manufacturers.
DE
DE: Display Enable: For those flat panels that
require an external display enable, this pin
provides a data enable.
PID0-PID3
Panel Sense: Inputs for panel-type selection.
I2DAT
I2C-bus data line.
I2CLK
I2C-bus clock line.
VDD_SRC
Internal not used
BACK_SRC
Internal not used
GND
Ground.
