886LCD-M Family
KTD-00474-U
Public User Manual
Date: 2010-06-22 Page
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CBE#[3:0]
Command/Byte Enable.
During FRAME# Operation:
During the address phase of a transaction, the G_CBE[3:0]#
signals define the bus command. During the data phase, the G_CBE[3:0]# signals are used as
byte enables. The byte enables determine which byte lanes carry meaningful data. The
commands issued on the G_CBE# signals during FRAME#-based AGP transactions are the
same G_CBE# command described in the PCI 2.2 specification.
During PIPE# Operation:
When an address is enqueued using PIPE#, the C/BE# signals carry
command information. The command encoding used during PIPE#- based AGP is
different
than
the command encoding used during FRAME#-based AGP cycles (or standard PCI cycles on a
PCI bus).
During SBA Operation:
These signals are not used during SBA operation.
PAR
Parity.
During FRAME# Operation:
G_PAR is driven by the GMCH when it acts as a FRAME#-based
AGP initiator during address and data phases for a write cycle, and during the address phase for
a read cycle. G_PAR is driven by the GMCH when it acts as a FRAME#-based AGP target
during each data phase of a FRAME#-based AGP memory read cycle. Even parity is generated
across G_AD[31:0] and G_CBE[3:0]#.
During SBA and PIPE# Operation:
This signal is not used during SBA and PIPE# operation.
Hub Interface signals
HL[10:0]
Packet Data:
Data signals used for HI read and write operations.
HLSTB
Packet Strobe:
One of two differential strobe signals used to transmit or receive packet data
over HI.
HLSTB#
Packet Strobe Complement
: One of two differential strobe signals used to transmit or receive
packet data over HI.
Clocks
CLKIN
Input Clock:
66-MHz, 3.3-V input clock from external buffer DVO/Hub interface.
DVOBCLK
DVOBCLK#
Differential DVO Clock Output:
These pins provide a differential pair reference clock that can
run up to 165-MHz. DVOBCLK corresponds to the primary clock out. DVOBCLK# corresponds to
the primary complementary clock out. DVOBCLK and DVOBCLK# should be left as NC (“Not
Connected”) if the DVO B port is not implemented.
DVOCCLK
DVOCCLK#
Differential DVO Clock Output
: These pins provide a differential pair reference clock that can
run up to 165-MHz. DVOCCLK corresponds to the primary clock out. DVOCCLK# corresponds to
the primary complementary clock out. DVOCCLK and DVOCCLK# should be left as NC (“Not
Connected”) if the DVO C port is not implemented.
DVOBCCLKINT
DVOBC Pixel Clock Input/Interrupt:
This signal may be selected as the reference input to
either dot clock PLL (DPLL) or may be configured as an interrupt input. A TV-out device can
provide the clock reference. The maximum input frequency for this signal is 85 -MHz. DVOBC
Pixel Clock Input: When selected as the dot clock PLL (DPLL) reference input, this clock
reference input supports SSC clocking for DVO LVDS devices. DVOBC Interrupt: When
configured as an interrupt input, this interrupt can support either DVOB or DVOC.
DVOBCCLKINT needs to be pulled down if the signal is NOT used.
DPMS
Display Power Management Signaling:
This signal is used only in mobile systems to act as the
DREFCLK in certain power management states(i.e. Display Power Down Mode); DPMS Clock is
used to refresh video during S1-M. Clock Chip is powered down in S1-M. DPMS should come
from a clock source that runs during S1-M and needs to be 1.5 V. So, an example would be to
use a 1.5-V version of SUSCLK from ICH4-M.
