Kontron 3.5-SBC-APL, User Manual

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3.5-SBC-APL – Rev. 0.1
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Pin Signal Type Note
6 GND PWR
7
+5 V PWR Max. 0.5 A
8 GND PWR
9
LCDVCC PWR Max. 0.5 A
10 LCDVCC PWR Max. 0.5 A
11 DDC CLK OT 4.7 KΩ, 3.3 V
12 DDC DATA OT 4.7 KΩ, 3.3 V
13 BKLTCTL OT 3.3 V level
14 VDD ENABLE OT 3.3 V level
15 BKLTEN# OT 3.3 V level
16 GND PWR Max. 0.5 A
17 LVDS A0- LVDS
18 LVDS A0+ LVDS
19 LVDS A1- LVDS
20 LVDS A1+ LVDS
21 LVDS A2- LVDS
22
LVDS A2+ LVDS
23 LVDS ACLK- LVDS
24
LVDS ACLK+ LVDS
25 LVDS A3- LVDS
26
LVDS A3+ LVDS
27 GND PWR Max. 0.5 A
28 GND PWR Max. 0.5 A
29 LVDS B0- LVDS
30 LVDS B0+ LVDS
31 LVDS B1- LVDS
32 LVDS B1+ LVDS
33 LVDS B2- LVDS
34 LVDS B2+ LVDS
35 LVDS BCLK- LVDS
36 LVDS BCLK+ LVDS
37 LVDS B3- LVDS
38 LVDS B3+ LVDS
39 GND PWR Max. 0.5 A
40 GND PWR Max. 0.5 A
Signal Description
LVDS A0…A3
LVDS A Channel data
LVDS ACLK
LVDS A Channel clock
LVDS B0…B3
LVDS B Channel data
LVDS BCLK
LVDS B Channel clock
BKLTCTL
Backlight control, PWM signal to implement voltage in the range 0 V-3.3 V
BKLTEN#
Backlight Enable signal (active low)
VDD ENABLE
Output display enable
LCDVCC
VCC supply to the display. 5 V or 3.3 V (1 A maximum) selected in BIOS setup menu.
Power sequencing depends on LVDS panel selection.
DDC CLK
DDC Channel Clock
GND
Power Supply GND signal