Keysight M5300A, Startup Manual

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M5300A PXIe RF AWG Modules Startup Guide 23
Overview on M5300A PXIe RF AWG Modules 1
The RSP is that portion of the BSP that allows you to control your target
FPGA. It provides an API that you can use to download and verify your
FPGA bit image. You may use the RSP to load design images onto the
hardware and perform simple register and streaming accesses to one or
more sandboxes.
The FPGA design consists of two regions: the static region and the
sandbox region. The static region for each supported module is defined
within BSP and cannot be modified. This region defines the
implementation of the FPGA interfaces to external resources, and defines
the interfaces to the sandbox. A static region implementation can define
one or more sandbox regions in an FPGA design. The sandbox region
contains the user specific FPGA design. The interface of the sandbox
depends on the static region implementation. A specific design flow is
promoted by PathWave FPGA, called Partial Reconfiguration (PR). In a PR
flow, a full FPGA reconfiguration is only necessary once for a given static
region version. The sandboxes can be reconfigured anytime, without a full
reconfiguration, and without stopping the current operation of the FPGA.
To perform FPGA designing, the BSP must be installed on the same
machine as the PathWave FPGA software. Both PathWave FPGA software
and the BSP function together and cannot be used individually.
To control the front panel IO on the M5300A modules, the M5300x API
allows you to control the hardware.
For more information regarding the PathWave FPGA interface available for
the Board Support Package corresponding to the M5300A module, refer to
the respective help file embedded in the PathWave FPGA software.