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Keysight M8132A 640 GSa/s Digital Signal Processor User’s Guide

Soft Front Panel

•

Selftests

- This option tests whether the particular ODI port is

functional or not. Connect a loopback connector to the respective port

and run a self-test. It will test whether the port allows proper

transmission of data. The test reports the connection status, and in

case of failure, the status of each individual lane. All failed test steps

are shown. Possible errors are PLL lock failures, burst, overflow,

underflow, CRC, and alignment errors.

Summary of Contents for M8132A

Page 1: ...User s Guide Keysight M8132A 640 GSa s Digital Signal Processor...

Page 2: ...n No additional government requirements beyond those set forth in the EULA shall apply except to the extent that those terms rights or licenses are explicitly required from all providers of commercial...

Page 3: ...is apparent or if an instrument does not pass the operator s checks notify the nearest Keysight Technologies Sales Service Office WARNING To avoid hazardous electrical shock do not perform electrical...

Page 4: ...made inoperative and secured against unintended operation until they can be repaired by qualified service personnel Ground the Instrument To minimize shock hazard the instrument chassis and cover must...

Page 5: ...tification mark to demonstrate that the equipment is Class A suitable for professional use and is for use in electromagnetic environments outside of the home Indicates that anti static precautions sho...

Page 6: ...the year when the design was proven This product complies with all relevant directives Universal recycling symbol This symbol indicates compliance with the China standard GB 18455 2001 as required by...

Page 7: ...ed label indicates that you must not discard this electrical electronic product in domestic household waste Product Category With reference to the equipment types in WEEE Directive Annex I this produc...

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Page 9: ...duction M8132A Overview 17 Key Features 17 Instrument Options 18 Front Panel 18 Related Documents 20 Additional Documents 20 2 Software Installation 3 Soft Front Panel Launching the Soft Front Panel 2...

Page 10: ...132A 6 Remote Programming Remote Programming Overview 50 Instructions 50 Instruction Header 50 White Space Separator 50 Braces 51 Ellipsis 51 Square Brackets 51 Program Data 51 Status Commands 52 STAT...

Page 11: ...NEXT 63 SYSTem HELP HEADers 63 SYSTem LICense EXTended LIST 64 SYSTem SET 64 SYSTem VERSion 65 SYSTem COMMunicate 65 SYSTem COMMunicate INSTr NUMBer 65 SYSTem COMMunicate HISLip NUMBer 66 SYSTem COMM...

Page 12: ...RESet 70 INSTrument FPGA DIRect DWORd 70 INSTrument FPGA DIRect BLOCk 71 INSTrument FPGA GEARbox CLEar 71 INSTrument FPGA GEARbox STARt 72 Current and Power Monitor Commands 73 INSTrument MONitor CURR...

Page 13: ...M CONFigure 77 INSTrument SANDbox M RLISt 78 INSTrument SANDbox M RINFo 78 INSTrument SANDbox M PEEK 78 INSTrument SANDbox M POKE 79 INSTrument SANDbox M SREad 79 INSTrument SANDbox M SREad BLOCk 79...

Page 14: ...NAME 84 ODI PORT N CAPability RATes 85 ODI PORT N CAPability RBMax 85 ODI PORT N CAPability TBMax 85 ODI PORT N CAPability TRMatch 86 ODI PORT N NAME 86 ODI PORT N ACTivate 86 ODI PORT N DEACtivate 87...

Page 15: ...Setup DSP 97 Usage 97 PathwaveLoopThrough 98 Cabling of DSP Connectors 98 Setup DSP 98 Usage 98 Optional Parameters 99 SimpleRspCapture 100 Cabling of DSP Connectors 100 Setup DSP 100 Usage 100 Contin...

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Page 17: ...M8132A is a 640 GSa s Digital Signal Processor Key Features The M8132A Digital Signal Processor provides the following key features Two large Xilinx Ultrascale VU9P FPGAs fully usable for custom proce...

Page 18: ...g an external pulse generator can be connected The FPGA designer has access to the Trigger Input signal inside both FPGA and may implement desired functionality The Trigger Input functionality is for...

Page 19: ...t 0 to 4 is configured as input bit 5 to 9 is configured as output The Control In Out is connected with the sandbox ports of the FPGAs LEDs The M8132A front panel include the following LEDs Status LED...

Page 20: ...ital Signal Processor use one of the following methods CD Browse the product CD for M8132A documentation Start All Programs Keysight M8131 Keysight M8131 Documentation Provides links to all product do...

Page 21: ...igital Signal Processor package is installed along with the M8131A Digitizer package using the same installer Therefore all prerequisites and installation procedure for M8132A module is the same as th...

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Page 23: ...al Processor User s Guide 3 Soft Front Panel Launching the Soft Front Panel 24 Command Line Arguments 27 Communication 28 Soft Front Panel 30 Clock Tab 36 IOs Tab 37 System Monitor Tab 40 This chapter...

Page 24: ...select the discovered M8132 module select the Installed Software tab and press the Soft Front Panel icon Please note that only instruments connected via PCIe are shown in the Keysight Connection Expe...

Page 25: ...eysight M8132A 640 GSa s Digital Signal Processor User s Guide 25 Soft Front Panel 3 Figure 3 M8132A in simulation mode Next a software startup screen will be displayed as shown in Figure 4 on page 26...

Page 26: ...26 Keysight M8132A 640 GSa s Digital Signal Processor User s Guide 3 Soft Front Panel Figure 4 M8132A startup screen...

Page 27: ...not specified with HiSLIP HiSLIP hislipNumber Set the instrument number for HiSLIP SCPI communication If not specified the same number as for VXI 11 3 is used AutoID Automatically select ports and nu...

Page 28: ...disabled the Soft Front Panel tries to start the servers on two consecutive ports socket port telnet port 1 AutoID Automatically select ports and number for the connections which are unique per instru...

Page 29: ...alues specified with Socket Telnet Inst HiSLIP or their respective default values instead If both NoAutoID and AutoID are specified AutoID overrides NoAutoID NOTE Ports may already be in use by Window...

Page 30: ...anel and its elements are illustrated in the following figure Figure 5 M8132A user interface The Soft Front Panel includes the following elements 1 Title Bar 2 Menu Bar 3 Tabs Clock IOs and System Mon...

Page 31: ...The menu bar includes the following pull down menus File View Utilities Tools Help Each menu and its options are described below File Menu The File menu includes the following selections File Connect...

Page 32: ...rument reads the state and updates all fields Utility Self Test Opens a window to start the self test and display the result after completion Not functional in the current software release Tools Clock...

Page 33: ...xamples directory Help Online Support Opens the instrument s product support web page Help About Displays product information including version number build date build info installed licenses availabl...

Page 34: ...s i e notification type time stamp and description It has the following controls signs and columns Clear All Click this button to clear all the errors from the errors list window Open On Error Click t...

Page 35: ...trument is connected Connected Instrument resource string An instrument is connected The resource string for example PXI36 0 0 INSTR is displayed Simulation Mode No real instrument is connected The us...

Page 36: ...de 3 Soft Front Panel Clock Tab The Clock tab provides the clock settings to M8132A module Figure 7 Clock tab Input Clock Settings Ref Clock Source A clock reference input is provided on the front pan...

Page 37: ...Keysight M8132A 640 GSa s Digital Signal Processor User s Guide 37 Soft Front Panel 3 IOs Tab The IOs tab provides input and output settings for optical data interfaces Figure 8 IOs tab...

Page 38: ...Band In band flow control RX Flow Control Select an option for the receive flow control The following options are available None No flow control In Band In band flow control Statistics Display the ODI...

Page 39: ...or not Connect a loopback connector to the respective port and run a self test It will test whether the port allows proper transmission of data The test reports the connection status and in case of fa...

Page 40: ...overcurrent and overtemperature To ensure that the operation remains within limits the user can measure the power consumption of the FPGAs in the System Monitor Tab Such a query is recommended every...

Page 41: ...Keysight M8132A 640 GSa s Digital Signal Processor User s Guide 4 Control In Out Control In Out and Trigger Input 42 This chapter describes the Control In Out and Trigger Input...

Page 42: ...ral purpose pins GP_TRIG_IN 0 2 as input ports and GP_TRIG_OUT 0 2 as output ports The front panel input ports Control In Out 0 4 and the trigger input Trig In can be routed to GP_TRIG_IN 0 2 and the...

Page 43: ...l In 0 to both FPGAs the connected signal is synchronized to the 200 MHz clock So there is an input accuracy of 5ns Once synchronized to this clock the transmission is cycle accurate which means that...

Page 44: ...orresponding bit positions inside the selector field in the soft front panel are specified in the following table Table 6 Bit Positions for Output Ports of the Output Multiplexer of the Switch Matrix...

Page 45: ...Input The trigger input Trig In is connected to a trigger generator that produces a trigger pulse on each rising edge of the connected input signal The trigger threshold can be set via remote program...

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Page 47: ...e FPGA KF9000A must be used as the design tool to program the sand box of the Xilinx FPGA inside the M8132A Additional documentation can be found at http www keysight com products KF9000A for KF9000A...

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Page 49: ...verview 50 Status Commands 52 Latency Calibration Commands 58 Common Commands 60 System Commands 63 Time Base Commands 68 Instrument Commands 69 FPGA Access Commands 70 Current and Power Monitor Comma...

Page 50: ...e command or query to be sent The program data which provides additional information to clarify the meaning of the instruction Instruction Header The instruction header is one or more command mnemonic...

Page 51: ...preceding element may be repeated one or more times Square Brackets Items enclosed in square brackets are optional Program Data Program data is used to clarify the meaning of the command or query It...

Page 52: ...er There is no buffering in this register while an event bit is set subsequent events corresponding to that bit are ignored This is a read only register Once a bit is set it remains set until cleared...

Page 53: ...7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 QUEStionable Status Error Event Queue Standard Event Status Register Status Byte Operation Complete Query Error Execution Error Command Er...

Page 54: ...the output buffer including any pending queries will clear the Message Available bit To set the enable register mask and generate an SRQ service request you must write a decimal value to the register...

Page 55: ...r Table 9 Questionable data register Bit Number Decimal Value Definition 0 Not used 1 Returns 0 1 Not used 2 Returns 0 2 Not used 4 Returns 0 3 Not used 8 Returns 0 4 Not used 16 Returns 0 5 Reference...

Page 56: ...onable REFClock PTRansition Table 10 Reference clock status register Connection Status Subsystem The Connection Status register contains the state of the USB connection to the M8132A module The follow...

Page 57: ...ight M8132A 640 GSa s Digital Signal Processor User s Guide 57 Remote Programming 6 Table 11 Connection status register Bit Number Decimal Value Definition 0 USB disconnected 1 USB module connection s...

Page 58: ...Description This command sets the Least Common Multiple LCM period value to be used for core clock phase alignment On the master module this value determines the frequency of the signal sent out at th...

Page 59: ...e core clock slave SSYNc Stop the clock signal generation at Sync Out master ARMadjust Arm the module for latency adjustment slave When the master starts sending data over the ODI the latency is measu...

Page 60: ...ears the error queue and cancels a OPC operation It doesn t clear the enable register ESE Enable bits in the Standard Event Status Register to be reported in the Status Byte The selected bits are summ...

Page 61: ...the register The selected bits are summarized in the Master Summary bit bit 6 of the Status Byte Register If any of the selected bits change from 0 to 1 a Service Request signal is generated The SRE...

Page 62: ...settings learn string You can then send the string back to the instrument to restore this state later For proper operation do not modify the returned string before sending it to the instrument Use SYS...

Page 63: ...tored until you remove errors from the queue If no errors have occurred when you read the error queue the instrument responds with 0 No error The error queue is cleared by the CLS command when the pow...

Page 64: ...EXTended LIST Query SYSTem LICense EXTended LIST Description The query lists the licenses installed Example Query SYST LIC EXT LIST SYSTem SET Command SYSTem SET binary block data Description In quer...

Page 65: ...is is only useful if there is more than one Keysight module connected to a PC otherwise one would normally use the default connections HiSLIP and VXI 11 instrument number 0 socket port 5025 telnet por...

Page 66: ...The query returns the socket port used by the Soft Front Panel Example Query SYST COMM SOCK SYSTem COMMunicate TELNet PORT Command SYSTem COMMunicate TELNet Description The query returns the telnet p...

Page 67: ...e LIST Command SYSTem LICense LIST Parameters None Description This query returns the complete details of the licenses installed Examples Query SYST LIC LIST M8070A CAL SYSTem LICense SUBScription DAT...

Page 68: ...lowing errors are detected when an external reference clock source is selected Amplitude of external reference signal too small or no signal Frequency of external reference signal out of range These e...

Page 69: ...Returned Format INSTrument SLOT NUMBer slot_number NL INSTrument IDENtify Command INSTrument IDENtify seconds Description The command identifies the instrument by flashing the green Access LED on the...

Page 70: ...ription The command loads the default image into the FPGA A Selects FPGA A for update B Selects FPGA B for update INSTrument FPGA DIRect DWORd Command INSTrument FPGA DIRect DWORd A B address value De...

Page 71: ...arated value list to be written at the address in the FPGA Query INSTrument FPGA DIRect BLOCk A B address number of values The query reads a list of values at an arbitrary address in the FPGA Returned...

Page 72: ...ox STARt Command INSTrument FPGA GEARbox STARt A B channel mask Description The command starts the gearbox for the data path channels in the selected FPGA A Selects FPGA A B Selects FPGA B channel mas...

Page 73: ...r CURRent MGTAVCC Query INSTrument MONitor CURRent MGTAVCC A B Description The query returns the current measured at MGTAVCC in the selected FPGA A Selects FPGA A B Selects FPGA B Returned Format INST...

Page 74: ...or POWer TOTal Query INSTrument MONitor POWer TOTal A B Description The query returns the total power consumed by an FPGA which is the sum of the powers measured at VCCINT MGTAVCC and MGTAVTT A Select...

Page 75: ...in the selected FPGA A Selects FPGA A B Selects FPGA B Returned Format INSTrument MONitor POWer MGTAVTT value Example INST MON POW MGTAVTT 2 0E 01 INSTrument MONitor POWer VCCINT Query INSTrument MONi...

Page 76: ...E M8132_A INSTrument SANDbox M FNAMe Query INSTrument SANDbox M FNAMe Description The query returns the name of the FPGA hosting the sandbox M An integer 1 for FPGA A 2 for FPGA B Returned Format INST...

Page 77: ...ANDbox M SID Description The query returns the Static Region ID of the FPGA hosting the sandbox M An integer 1 for FPGA A 2 for FPGA B Returned Format INSTrument SANDbox M SID name Example INSTrument...

Page 78: ...Query INSTrument SANDbox M RINFo name Description The query returns for a register name address length access type M An integer 1 for FPGA A 2 for FPGA B name The name of the register Returned Format...

Page 79: ...ent SANDbox M SREad Query INSTrument SANDbox M SREad index size Description Not yet supported M An integer 1 for FPGA A 2 for FPGA B index The stream index size The read size in bytes Returned Format...

Page 80: ...NDbox1 SWRite INSTrument SANDbox M SWRite BLOCk Command INSTrument SANDbox M SWRite BLOCk index csv_block Description Not yet supported M An integer 1 for FPGA A 2 for FPGA B index The stream index cs...

Page 81: ...REad address_or_name size Description Not yet supported M An integer 1 for FPGA A 2 for FPGA B address_or_name The address or name of the memory size The read size in bytes Returned format INSTrument...

Page 82: ...or FPGA B address_or_name The address or name of the memory binary_block The data block in binary format Example INSTrument SANDbox1 MWRite INSTrument SANDbox M MWRite BLOCk Command INSTrument SANDbox...

Page 83: ...ml ODI ACHannels Query ODI ACHannels Description The query returns the usable optical channels as a string The channel names are separated by commas N An integer to select the ODI port 1 4 Return Form...

Page 84: ...lity FCONtrols flow control list NL flow control list NONE IBANd IBPChannel OOBWire OOBBplane M M An integer 0 13 Example ODI PORT1 CAP FCON NONE IBANd ODI PORT N CAPability LANes Query ODI PORT N CAP...

Page 85: ...41 ODI PORT N CAPability RBMax Query ODI PORT N CAPability RBMax Parameters None Description The query returns the supported receiver maximum burst values Return Format ODI PORT N CAPability RBMax bur...

Page 86: ...Parameters None Description The query returns the name of the port Return Format ODI PORT NAME name NL Example ODI PORT NAME ODI1 ODI PORT N ACTivate Command ODI PORT N ACTivate lane_rate tx_burst_ma...

Page 87: ...ort is active this query returns the parameter values used in the command to activate the port ODI PORT N DEACtivate Command ODI PORT N DEACtivate Description The command switches off the optical port...

Page 88: ...se troubleshoot the receive path starting with RxSignalLoss RxReady 2 Receiver ready All lanes synchronized and aligned RxLaneError 3 Error in one or more lanes since last GetStatus RxBurstMaxError 4...

Page 89: ...T N PSTatistics RBYTes Parameters None Description This query returns the number of bytes received by the ODI port Example ODI PORT1 PST RBYT integer ODI PORT N PSTatistics TBYTes Query ODI PORT N PST...

Page 90: ...econd one represents the 21 bit register of the Output Mux Table 13 Bit Positions for output ports of the Input Multiplexer Table 14 Bit Positions for output ports of the Output Multiplexer Bit Positi...

Page 91: ...ped to all Mux outputs Further mappings are provided in the following tables Table 15 Mapping between input and output ports of the Input Multiplexer Table 16 Mapping between input and output ports of...

Page 92: ...and Output Multiplexers Two possible values are ON 1 Mux outputs are forced to 0 OFF 0 default Mux outputs carry signal of the mapped inputs Query CIOut MUX CLR Description The query returns two comm...

Page 93: ...ST Commands TEST PON Query TEST PON Parameters None Description This query returns the result of the power on self tests Example Query TEST PON TEST TST Query TEST TST Parameters None Description This...

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Page 95: ...8132A 640 GSa s Digital Signal Processor User s Guide 7 Examples Introduction 96 PathwaveCapture 97 PathwaveLoopThrough 98 SimpleRspCapture 100 Continuous Streaming with Deterministic Latency to DSP M...

Page 96: ...ole applications and are provided as Microsoft Visual Studio 2019 solutions PathwaveCaptureExample example is written in C and uses the VISA NET library to control the instrument over SCPI The Pathwav...

Page 97: ...3 channel 3 received data is re transmitted on channel 1 A data transmit source is configured on channels 2 and 4 and capture is configured on channel 2 Data captured is then verified and displayed C...

Page 98: ...ls 2 and 4 and capture is configured on channel 2 The multiplexer can be configured through program arguments to resize combine or split packets as they pass through The program will verify that the e...

Page 99: ...th_sync bit in DPU_MUX_CONTROL resizeEnable Default 0 Enable resize test mode resizePacketLength1st Default 1000 New packet size created by path on DPU 2 or 1 if reverseDirection in units of 64 bytes...

Page 100: ...RSP interface and interact with registers accessed via Pathwave build meta data Cabling of DSP Connectors Not applicable Setup DSP Before starting the example program start the M8132A Soft Front Pane...

Page 101: ...ignal Processor User s Guide 101 Examples 7 Continuous Streaming with Deterministic Latency to DSP Module Refer to Keysight M8131A 16 32 GSa s Digitizer User s Guide The User s Guide of the M8131A inc...

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Page 103: ...mance Specification The performance specification can be found in the Data Sheet of the M8132A at http www keysight com find M8132A Operating Environment Storage Temperature 40 C to 70 C Operating Tem...

Page 104: ...rate the instrument in the presence of flammable gases fumes or powders Operation of any electrical instrument in such an environment constitutes a definite safety hazard Power consumption 280 W nom S...

Page 105: ...menu 33 I Instrument Commands 69 IOs Tab 37 K Key Features 17 M M8132A Digital Signal Processor 17 M8132A Overview 17 Mass Memory Commands 63 Menu bar 31 O Operating Environment 103 Optical Data Inter...

Page 106: ...This information is subject to change without notice Keysight Technologies 2020 Edition 2 0 May 2020 www keysight com...

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