Kenwood TS-5700, Service Manual

Page: 38 / 91

SEMICONDUCTOR DATA
A/D, D/A Converter : AK4506-VS (Control U n it IC504)
• Terminal connection diagram
• Block diagram
1
0
VA AGND
VD VB DGND MCLK CMODE
AINA+
2a
VAEF
AINA- 2 27 VA
27 26 16 17 15
11 19
AINL+ 3
26 AGND
Clock Divider
AINL- 4 25 AO UTA+
AINL+
6I
Decimation
TST1 5
24 AO UTA- AINL-
Modulator Filter
TST2 6 23 AOUTL+
12
LJR
TST3 7 22 AOUTL-
AINA+ Decimation
13 SCLK
TST4
a
21 DFSO
AINA-
Filter
PD-AD 9 20 DFS1
14 SOTO
PD-DA
Serial
1/0 10 19 CM ODE
VAEF
Interface
1a SDTI
MCLK 11
1
a
SDTI
LJR
12 17 VB
AOUTL+
6I
ax
5 TST1
SCLK 13 16 VD
AOUTL-
Modulator lnterpolator
6 TST2
SOTO 14 15 DGND De-emphasis 7
Control
TST3
AOUTA+
6I
ax
a
AOUTR-
Modulator lnterpolator
TST4
9
10
21
PD-AD PD-DA DFSO
DFS1
• Terminal function
Pin No.
Name 1/0 Fu nction
1 A I N R + I R i g ht-c h a n n e l a n a log positive i n p ut p i n
2 A I N R- I R i g ht-c h a n n e l a n a l o g negative i n put p i n
3 A I N L+ I Left-c h a n n e l a n a log positive i n put p i n
4 A I N L- I Left-c h a n n e l a n a log n egative i n put p i n
5 TST 1 I Test p i n ( P u l l d own p i n )
6 TST2 I Open or co n n ect to AG N D .
7 TST3 0 Test p i n
8 TST4 0 O p e n
9 P D AD I
Power down p i n .
P D A D : A D C power down p i n , PD DA: DAC power down p i n
1 0 P D DA I W h e n each p i n is low, t h e correspon d i n g part e nters t h e power down mode. W h e n the power t u r n s o n ,
resett i n g a n d c a l i brati o n m ust be carried o u t . Resett i n g i s performed b y m a k i n g both P D A D a n d P D DA low.
1 1 M C L K I Master clock i n put p i n .
1 2 L/R I I n put/output c h a n n e l s e l ect p i n . T h e f s clock i s i n put. H i g h : Left c ha n n e l ; Low: R ig h t c h a n n e l
1 3 S C L K I Serial data clock p i n . O n e b i t o f data i s output at a fa l l i n g edge o f t h e s i g n a l at t h i s p i n .
1 4 S OTO 0 Serial data output p i n . Data i s two ' s complement. T h e M S B i s output fi rst, a n d 1 6 bits a re output b y l eft
j u stificat i o n . Goes low afte r 1 6 b its a re output. Low w h e n t h e power i s down ( P D A D : Low) .
1 5 D G N D
-
D i g i t a l u n i t g ro u n d p i n
1 6 VD
-
D i g ita l u n it power s u pply p i n ( + 5V)
1 7 VB
-
S i l icon P C B powe r s u pply p i n ( + 5V)
1 8 S DT I I S e r i a l data i n put p i n .
Data i s two ' s c o m p l e m e n t . The MSB is output fi rst, a n d 1 6 bits a re output by right j u stificati o n .
1 9 C M O D E I Master clock s e l ect p i n ( P u l ldown p i n )
Low : M C L K = 2 56fs, H ig h : M C L K=384fs
2 0 D F S 1 I D e e m p h a s i s freq u e n cy s e l ect p i n
2 1 D FSO I S u p p o rts th ree freq u e n c i e s .
2 2 AOUTL- 0 Left-c h a n n e l a n a log n egative output p i n
2 3 A O U T L + 0 Left-c h a n n e l a n a log positive output p i n
2 4 AOUTR- 0 R i g ht-c h a n n e l a n a log n egative output p i n
2 5 A O U T R + 0 R i g ht-c h a n n e l a n a log positive output p i n
2 6 AG N D
-
Analog g ro u n d p i n
2 7 VA
-
A n a l og power s u pply p i n ( + 5V)
2 8
V R E F 0 Reference voltage output p i n VA-3 . 0V
Output accord i n g to the VA refe rence.
The 1 OµF e l ectrolytic capacitor a n d 0 . 1 µF cera m i c capacitor a re
c o n n e cted between V R E F a n d VA.
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