TS-5700
CIRCUIT DESCRIPTION
PLL Circu it
The TS-570D PLL circuit consists of a PLL loop that
includes a DDS that covers a frequency range 30kHz
to 30MHz in 1 OHz or 1 Hz steps according to the
20MHz reference frequency, a DDS circuit that gener
ates CAR and a PLL loop that produces L02.
The divide ratio data to each PLL loop and DDS data
are controlled by a microprocessor. Each loop is con
trolled by a single crystal frequency control system
based on the reference frequency fsrn. (See the PLL
block diagram in Figure 2.)
• Reference Sig n a l Generation Circuit
The reference frequency fSTD used for frequency
control is produced by the 20MHz crystal oscillator
(X500 and 0500: 2SC271 4(Y)). It is used as the refer
ence signal fREF for the PLL IC and DDS1 in the PLL
unit.
The 1 OM Hz signal divided by 2 by DDS1 goes to
DDS2 in the L01 generator. The signal also goes to
the CAR generator to produce a 8 .83MHz signal.
The crystal oscillator can be replaced by an optional
TCXO (S0-2). It is switched to the TCXO by cutting
lead resisters R503 and R504.
• L02
.·
0509: 2
.
SK1 975(V) in VC02 generates 64. 22MHz.
The 20MHz reference frequency fREF is supplied to
pin 1 5 of IC500: MB86001 PF, and is divided by 1 000
(4000 in FM mode) to produce a 20kHz (5kHz 1n FM
mode) comparison frequency.
The VC02 output is applied to pin 6 of IC500:
MB86001 PF and divided by 321 1 (1 2844 in FM mode)
The signal is compared with the 20kHz (5kHz in FM
mode) signal with the phase comparator. The VC02
frequency is locked. The divide ratio is transmitted
from the control unit.
The output from the PLL passes through buffer
051 O, amplified by amplifier 051 1 , 0546, and passes
through a low-pass filter. The impedance is converted
and the resulting signal is output to the RF unit as
L02.
•
L01
Three VCOs 0528, 0530, 0532: 2SK1 875(V)x3
generate 73.08MHz to 1 03.05MHz. The 20MHz refer
ence frequency is applied to pin 1 5 of PLL IC IC507:
MB86001 PF, and divided by 40 to produce a 500kHz
comparison frequency.
The output passes through the 0535 buffer. One
output is amplified by amplifier 0534: 2SC2714(Y) and
band-pass filter and goes to the RF unit. The other
output passes through buffer 0533: 2SC271 4(Y) and
goes to pin 5 of mixer IC506 : SN7651 4 . A signal of
65.54 to 66.04 MHz is input to pin 1 1 of IC506 to pro
duc
e
a signal of 7. 5 to 37MHz. The signal is output
from pin 1 3, passes through a low-pass filter, a high
pass filter, buffer 0523, and amplifier 0522 and goes
to pin 6 of IC507.
This signal is divided by N, and compared with the
500kHz signal with the phase comparator. The mixer
output frequency is locked in 500kHz steps. The di
vide ratio N is transmitted from the control unit as data
(N: 1 5 to 75) corresponding to 0 to 30MHz in 500kHz
steps. One of three VCOs is selected by the serial/
parallel IC IC1 4: NJU371 8G in the TX-RX unit accord
ing to the VCO change signals (VC01 A, VC01 B, and
VC01 C).
DDS2 (IC502: F71 022) generates a 540 to 1 040kHz
digital signal. It is converted to an analog signal by a
digital-to-analog converter consisting of CP502,
CP503, and 051 8, passes through a low-pass filter,
and goes to p
'
in 6 of IC504: UPC1 037GR. The 5MHz
signal produced by diving the 1 OM Hz reference fre
quency for the DDS2 by 2 goes to pin 8 of the mixer,
and a 5.54 and 6.04MHz signal is output from pin 2.
The output signal passes through a band-pass filter
and buffer 051 9, and input to pin 8 of mixer IC506 :
UPC1 686G. It is mixed with the 60MHz signal ob
tained by tripling 20MHz reference frequency fREF by
multiplying circuit 0521 to produce a 64.54- to
66.04MHz signal. This signal passes through a band-
pass filter, and goes to pin 1 1 of mixer IC506.
.
DDS2 sweeps the 540 to 1 040kHz digital signal 1n
1 O or 1 Hz steps. L01 covers 73.08 to 1 03.05MHz in
1 O or 1 Hz steps and is output as L01 to the RF unit.
• CAR
To generate the 8.83MHz signal used for local oscil
lation and detection, DDS1 (IC501 : F71 022) generates
a digital signal with the 1 .1 7MHz basic frequency. It is
converted to an analog signal by a digital-to-analog
converter consisting of CP500, CP501 , and 051 3. The
signal passes through a low-pass filter and goes to pin
6 of mixer IC503: UPC1 037GR. The 1 OM Hz chopper
output from DDS1 is input to pin 8 of the mixer and the
8.83MHz signal is output from pin 3.
The output signal passes through buffer 051 4. Un
wanted components are removed by a ceramic filter
consisting of CF500 and CF501 . The resulting signal
passes through amplifier 051 5, buffer 051 6, and a
low-pass filter, and is output to the RF unit as the CAR
signal.
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