![background image](http://html.mh-extra.com/html/kenwood/tk-8360/tk-8360_service-manual_191757015.webp)
TK-8360/8360H/8360H
(
U
)
15
4. PLL Frequency Synthesizer
The PLL circuit generates the fi rst local oscillator signal
for reception and the RF signal for transmission.
4-1. PLL Circuit
The frequency step of the PLL circuit is 5, 6.25, 10 or
12.5kHz.
A 19.2MHz reference oscillator signal is divided at IC2
by a fixed counter to produce the 5, 6.25, 10 or 12.5kHz
reference frequency. The voltage controlled oscillator (VCO)
output signal is buffer amplifi ed by Q12, then divided by a
programmable counter in IC2.
The divided signal is compared in phase with the 5, 6.25,
10 or 12.5kHz reference signal in the phase comparator in
IC2. The output signal from the phase comparator is fi ltered
through a low-pass fi lter and passed to the VCO to control
the oscillator frequency.
4-2. VCO Circuit
The operating frequency is generated by Q6 in transmit
mode and Q8 in receive mode. The oscillator frequency is
controlled by applying the VCO control voltage, obtained
from the phase comparator to the varactor diodes (D7 in
transmit mode and D9 in receive mode) and assist voltage
to the (D10, D12 and D13 in transmit mode and D11, D14
and D15 in receive mode).
The TX/RX pin is set high in receive mode causing Q7 to
turn off, and turn Q10 on. The TX/RX pin is set low in trans-
mit mode. The outputs from Q8 and Q6 are amplified by
Q12 and sent to the RF amplifi ers.
D7
D10,D12,D13
D11,D14,D15
ASTC
IC3
Assist
voltage
Q6
TX VCO
Q12
BUFF
AMP
D9
Q8
RX VCO
Q7,Q10
T/R SW
Charge
pump
OP
AMP
LPF
Phase
comparator
1/M
1/N
REF
OSC
19.2MHz
PLL
DATA
IC2: PLL IC
4-3. Unlock Circuit
During reception, the 9RC signal goes high, the 9TC sig-
nal goes low, and Q400 turns on. Q402 turns on and a volt-
age is applied to the collector (9R). During transmission, the
9RC signal goes low, the 9TC signal goes high and Q401
turns on. Q403 turns on and a voltage is applied to 9T.
The MCU in the control unit monitors the PLL (IC2) LD
signal directly. When the PLL is unlocked during transmis-
sion, the PLL LD signal goes low. The MCU detects this
signal and makes the 9TC signal low. When the 9TC signal
goes low, no voltage is applied to 9T, and no signal is trans-
mitted.
IC704
MCU
Q400
SW
Q402
SW
IC2
PLL
Q401
SW
Q403
SW
LD
9RC
9C
9R
9T
9TC
PLL lock
: LD “H”
Fig. 9 Unlock circuit
Fig. 8 PLL circuit
5. Control Circuit
The MCU carries out the following tasks:
1) Controls the WIDE, NARROW, TX/RX outputs.
2) Controls the Baseband IC (IC702).
3) Controls the PLL (IC2).
4) Controls the display unit.
IC1
LCD driver
BLED
C.DATA
SCLK
SLK
IRQ
CSN
Display unit
IC704
MCU
IC702
Baseband IC
GLED
RLED
MBL
BLC
LCDDI
LCDDO
LCDCL
LCDCE
IC2
PLL
PLLE
PLDT
PLCK
UL
Fig. 10 Control circuit
CIRCUIT DESCRIPTION
TENTATIVE