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KPCI-PIO32IOA and KPCI-PDISO8A User’s Manual
Installation
3-15
Combining output channels
In some applications, it may be desired to attempt parallel operation of multiple output channels
to provide a load current that is higher than specified for one individual output channel. With
some care and a good understanding of the limitations, this method can be used successfully
with the KPCI board output channels.
Whenever KPCI channels are operated in parallel, due consideration should be given to each
channel to ensure that each channel will remain operating within specified limits. Some items to
consider while attempting this mode of operation are: KPCI PCB layout, dynamic and steady-
state current unbalance, and temperature unbalances pertaining to the final circuit or system
configuration. The KPCI PCB layout has been designed to minimize stray passive and reactive
components where possible within each channel to the connector. These stray components are
generally not dominant when low-frequency operation of the isolated output channels is used.
General guidelines
•
Voltage equity of the channels is assured by the parallel configuration. However, under tran-
sient conditions, voltage differentials can appear across devices due to di/dt effects in
unequal stray inductances. Strive to reduce stray inductance to values that give acceptable
overshoots at the maximum operating current.
•
Cables should be reasonably matched for a given connector group of channels. Try to avoid
using significantly different cable lengths when paralleling channels that span cable connec-
tor groups.
•
The power source that is to be switched should be as “stiff” as possible. For example, a volt-
age source should have very low output impedance.
•
While software writes to the output channels will actuate each channel at nearly the same
time, do not assume that the output channels themselves will traverse their high-to-low
impedance characteristics at the same rates.
Steady-state current sharing
During the periods of time outside of the switching transitions, the current in a parallel group of
output MOSFET channels will distribute itself in the individual devices in inverse proportion to
their ON resistance. The channel with the lowest ON resistance will carry the highest current.
This will, to an extent, be self-compensating because the power loss in this channel will be the
highest. It will run the hottest, and the increase in ON resistance due to heating will be more than
that of the other channels, which will tend to equalize the current.
Precautions
Once the system is wired for use in an application, it is prudent to examine the switching behav-
ior of the paralleled channels in an offline test. This will ensure that, for the particular applica-
tion, there will be no unnecessary stresses to the system with the paralleled configuration. There
is no straightforward method for determining whether or not channel combining can be used
successfully in a particular application. The decision should be based on how well the system
channels can be matched, and how they are used with the particular sources and loads.
Channel combining cannot entirely avoid mismatches and during switching, transients and
stresses are placed on the KPCI output channels. Though these stresses may be minimized, they
may affect long-term reliability of the channels when high duty cycle operation is desired with
combined channels.
Summary of Contents for KPCI-PIO32IOA
Page 11: ...1 Overview...
Page 14: ...2 General Description...
Page 17: ...3 Installation...
Page 32: ...4 External Interrupts...
Page 36: ...5 Troubleshooting...
Page 52: ...A Specifications...
Page 57: ...B I O Address Mapping...
Page 64: ...C Glossary...