Keithley KPCI-PDISO8A, User Manual

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KPCI-PIO32IOA and KPCI-PDISO8A User’s Manual I/O Address Mapping B-7
Manipulating control and data registers
Be aware that software programming for a PCI board, such as the KPCI-PIO32IOA and KPCI-
PDISO8A, is more involved than for an ISA board. As mentioned in the
Appendix B introduc-
tion, DriverLINX eliminates the need for user interaction with control and data registers. How-
ever, control and data registers can be manipulated in the following special situations:
•
You are an advanced user needing to use the KPCI-PIO32IOA or KPCI-PDISO8A with an
operating system other than Microsoft Windows 98/Me or Windows NT 4.0, 2000, or XP or
greater. In this situation, you must write a new driver. This task requires an in-depth knowl-
edge of PCI-bus interfacing and your development operating system.
•
You want to program the KPCI-PIO32IOA or KPCI-PDISO8A at the register level using an
ActiveX hosting language. In this situation, you may use the “Direct I/O ActiveX Automa-
tion Object” that comes with DriverLINX. The Direct I/O ActiveX Automation Object
allows you to set the control and data registers directly and bypass the DriverLINX API, yet
avoids the full complexities of PCI bus interfacing. Refer to your DriverLINX manual for
more information.
•
You want to reuse, with the KPCI-PIO32IOA or KPCI-PDISO8A, an existing application
program that makes port I/O calls to an ISA-bus digital I/O board such as the PIO-96 or
PIO-24.
General approach to manipulating control and data registers
This subsection outlines some general program tasks needed to use the data and control registers
of the KPCI-PIO32IOA and KPCI-PDISO8A board.
• If the board is to transfer and process data upon receipt of external interrupts, the following
are set:
– Bit 12 of the interrupt control/status register, located at 0x38, is set to 1 to
configure the board for interrupt service.
– The interrupt-pending bit and the interrupt missed bit in BADDR0 are initialized to the
cleared condition by writing 1s to interrupt control/status register status bits 17 and 23 at
38. The polarity select bit is initialized to the clear condition by writing a 0
to the interrupt control/status register control bit 6.
• If you retrieve data using interrupts, the interrupt-pending bit and interrupt-missing bit must
be cleared by software at the conclusion of each interrupt-service (ISR) by writing ones
(Acknowledge) to interrupt control/status register bits 17 and 23 at base address 0 + 0x38.
The interrupt enable bit and interrupt polarity select bit of the interrupt control/status register
are cleared by writing zeros to bits 12 and 6.
• Input control registers are read only.
• Output registers have read/write capabilities. Writing to an output register changes the states
of the solid-state relays. Reading the output registers returns the states of the solid-state
relays.
• All input and output registers are static, and no configuration ability exists.