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B-4
I/O Address Mapping
KPCI-PIO32IOA and KPCI-PDISO8A User’s Manual
Control register bit functions
The control register bit functions for each port are identical. These functions are listed in
.
Interrupt control/status register
The firmware of the KPCI-PIO32IOA and KPCI-PDISO8A boards implement a 32-bit interrupt
control/status register. This register is located at 0x38 offset, where 0x designates
hexadecimal. A control bit of the interrupt control/status register is used to configure the board
for interrupt-based data transfer and processing. Two status bits are used to determine whether
one or more interrupts are pending or were missed during data processing. Two control bits pro-
vide for the selection of interrupt polarity (falling or rising edge) and the enabling/disabling of
the interrupt signal.
Interrupt control/status bit descriptions
The four interrupt control/status register bits are described in detail in
.
Table B-2
Control register bit functions for each port
Bit
Number
Function
Variable
Name
I/O Status for this Bit
Bit 6
Access Mode Select
N/A
Bit 6 Bit 5
0
0
= No input latching.
0
1
= Latch group on rising edge of
INT_REQ signal.
1
0
= No input latching.
1
1
= Latch group on falling edge of
INT_REQ signal.
Bit 5
Access Mode Select
N/A
Summary of Contents for KPCI-PDISO8A
Page 11: ...1 Overview...
Page 14: ...2 General Description...
Page 17: ...3 Installation...
Page 32: ...4 External Interrupts...
Page 36: ...5 Troubleshooting...
Page 52: ...A Specifications...
Page 57: ...B I O Address Mapping...
Page 64: ...C Glossary...