XV-NA7SL
35
5.8 MN102L62GLF3 (IC401) : Unit CPU
• Pin function
Pin No.
Symbol
I/O
Function
1
WAIT
I
Micon wait signal input
2
RE
O
Read enable
3
SPMUTE
O
Spindle muting output to IC251
4
WEN
O
Write enable
5
LMMUTE
-
Non connect
6
CS1
O
Chip select for ODC
7
CS2
-
Non connect
8
HDTYPE
O
HD Type selection
9
DRVMUTE
O
Driver mute
10
SBRK
O
Short brake terminal
11
LSIRST
O
LSI reset
12
WORD
I
Bus selection input
13
A0
O
Address bus 0 for CPU
14
A1
O
Address bus 1 for CPU
15
A2
O
Address bus 2 for CPU
16
A3
O
Address bus 3 for CPU
17
VDD
-
Power supply
18
SYSCLK
-
Non connect
19
VSS
-
Ground
20
XI
-
Not use (Connect to vss)
21
XO
-
Non connect
22
VDD
-
Power supply
23
OSCI
I
Clock signal input(13.5MHz)
24
OSCO
O
Clock signal output(13.5MHz)
25
MODE
I
CPU Mode selection input
26
A4
O
Address bus 4 for CPU
27
A5
O
Address bus 5 for CPU
28
A6
O
Address bus 6 for CPU
29
A7
O
Address bus 7 for CPU
30
A8
O
Address bus 8 for CPU
31
A9
O
Address bus 9 for CPU
32
A10
O
Address bus 10 for CPU
33
A11
O
Address bus 11 for CPU
34
VDD
-
Power supply
35
A12
O
Address bus 12 for CPU
36
A13
O
Address bus 13 for CPU
37
A14
O
Address bus 14 for CPU
38
A15
O
Address bus 15 for CPU
39
A16
O
Address bus 16 for CPU
40
A17
O
Address bus 17 for CPU
41
A18
-
Non connect
42
A19
-
Non connect
43
VSS
-
Ground
44
A20
-
Non connect
45
DISCSTP
O
Mechanism state signal output
46
HUGUP
O
Connect to pick-up
47
TCLOSE
-
Non connect
48
WOBBLEF1L
49
HFMON
O
HFM Control output to Q103
50
TRVSW
I
Detection switch of traverse in-
side
51
SWUPDN
-
Non connect
52
MECHA_H/V
-
Connect to ground
53
DISCSET
I
Mechanism state signal input
54
VDD
-
Power supply
55
FEPEN
O
Serial enable signal for FEP
56
SLEEP
O
Standby signal for FEP
57
BUSY
-
Non connect
58
REQ
O
Communication request
59
-
-
Connect to TP405
60
-
-
Non connect
61
VSS
-
Ground
62
EPCS
O
EEPROM chip select
63
EPSK
O
EEPROM clock
64
EPDI
I
EEPROM data input
65
EPDO
O
EEPROM data output
66
VDD
-
Power supply
67
SCLKO
O
Communication clock
68
S2UDT
I
Communication input data
69
U2SDT
O
Communication output data
70
CPSCK
O
Clock for ADSC serial
71
P74/SBI1
I
Not use (Pull down)
72
SDOUT
O
ADSC serial data output
73
-
I
Not use (Pull up)
74
-
I
Not use (Pull up)
75
NMI
I
NMI Terminal
76
ADSCIRQ
I
Interrupt input of ADSC
77
ODCIRQ
I
Interrupt input of ODC
78
DECIRQ
I
Interrupt input of ZIVA
79
CSSIRQ
I
Not use (Pull down)
80
ODCIRQ2
I
Interruption of system control
81
ADSEP
I
Address data selection input
82
RST
I
Reset input
83
VDD
-
Power supply
84
TEST1
I
Test signal 1 input
85
TEST2
I
Test signal 2 input
86
TEST3
I
Test signal 3 input
87
TEST4
I
Test signal 4 input
88
TEST5
I
Test signal 5 input
89
TEST6
I
Test signal 6 input
90
TEST7
I
Test signal 7 input
91
TEST8
I
Test signal 8 input
92
VSS
-
Ground
93
D0
I/O Data bus 0 of CPU
94
D1
I/O Data bus 1 of CPU
95
D2
I/O Data bus 2 of CPU
96
D3
I/O Data bus 3 of CPU
97
D4
I/O Data bus 4 of CPU
98
D5
I/O Data bus 5 of CPU
99
D6
I/O Data bus 6 of CPU
100
D7
I/O Data bus 7 of CPU
Pin No.
Symbol
I/O
Function
