DSP
BOARD
SCHEMATIC
DIAGRAM
3.5
FROM/TO
CCD
CN2
FROM/TO
CPU
CN3
NC
:
OPEN
SC92631
1.6
0
0.1
0.3
0
1.5
1.9
1.8
1.6
1.6
1.6
0
3.3
0.1
0.1
3.3
3.1
3.3
3.1
-7.0
-7.0
-0.3
0
-0.2
-6.6
-6.6
0.5
0.5
1.6
1.6
1.6
3.3
3.3
3.2
2.2
2.2
3.4
3.4
1.5
1.6
1.5
3.9
2.6
0.5
0.7
0
1.6
1.6
6.4
2.3
2.3
9.2
DSP
AD
CDS/AGC
V.DRIVER
AGC
10bit
ADC
OUTPUT
LATCH
CDS
CC
y
y
BLK
BLK
MTRX
D/A
D/A
MOD
1/4
1/n
1/2
1/m
BUF
F.F.
C
GMIX
C
GMIX
MTRX
GAIN
MTRX
MLTPLX
BUF
P/C
1H
DL
MLTPLX.
OB
CLAMP
PRE-
KNEE
DECODE
TIME-DIV.
LC1
LC2,
3
SSV2782-P107Z
X1
TP1
3-5
3-5
2C
3-5
SSV2782-P507Z
PAL
NC
10k
NC
R15
NTSC
10k
R16
33
0
R65
17.734475MHz
14.31818MHz
X1
L1
10
0
NC
R27
100
D3.3V
R41
1.2k
(Page
3-4)
(Page
3-9)
C23
100/10
C53
3p
NC
R30
NC
C52
NC
C53
R53
0