RX-8012VSL/RX-8010VBK
1-12
AK4112A (IC551) : 96kHz 24bit DIR
2. Block diagram
3. Pin Function
1. Pin Layout
1
DVDD
2
DVSS
3
TVDD
4
V/TX
5
XTI
6
XTO
7
PDN
8
R
9
AVDD
10
AVSS
11
RX1
12
RX2/DEF0
13
RX3/DEF1
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
RX4/DEF2
CM0/CDTO
CM1/CDTI
OCKS1/CCLK
OCKS0/CSN
MCKO1
MCKO2
DAUX
BICK
SDTO
LRCK
ERF
FS96
P/SN
AUTO
Top
View
Input
Selector
Clock
Recovery
DAIF
Decoder
System
Control
AC-3/MPEG
Detect
Error
Detect
Clock
Generator
X'tal
Oscillator
96kHz
Detect
Audio
I/F
uP I/F
DEM
RX1
RX2
RX3
RX4
DVDD
DVSS
PDN
V/TX
AVSS
AUTO
ERF
P/S="L"
AVDD
R
MCKO1 MCKO2
XTI
XTO
FS96
DAUX
TVDD
LRCK
BICK
SDTO
CSN
CCLK
CDTO
CDTI
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Pin Name
DVDD
DVSS
TVDD
V
TX
XTI
XTO
PDN
R
AVDD
AVSS
RX1
DIF0
RX2
DIF1
RX3
DIF2
RX4
AUTO
Function
Digital Power Supply Pin, 3.3V
Digital Ground Pin
Input Buffer Power Supply Pin, 3.3V or 5V
Validity Flag Output Pin in parallel mode
Transmit channel (through data)
Output Pin in serial mode
X'tal Input Pin
X'tal Output Pin
Power-down mode Pin
When "L", the AK4112A is powerd-down and reset.
External resister pin
/-1% resistor to AVSS externally.
Analog Power Supply Pin
Analog Ground pin
Receiver Channel 1
This channel is selected in parallel mode
or default of serial mode.
Audio Data Interface format 0 Pin in parallel mode
Receiver Channel 2 in serial mode
Audio Data Interface format 1 Pin in parallel mode
Receiver Channel 3 in serial mode
Audio Data Interface format 2 Pin in parallel mode
Receiver Channel 4 in serial mode
Non-PCM Detect Pin
"L": No detect, "H": Detect
I/O
-
-
-
O
O
I
O
I
-
-
-
I
I
I
I
I
I
I
O
No.
16
17
18
19
20
21
22
23
24
25
26
27
28
Pin Name
P/S
FS96
ERF
LRCK
SDTO
BICK
DAUX
MCKO2
MCKO1
OCKS0
CSN
OCKS1
CCLK
CM1
CDTI
CM0
CDTO
Function
Palrallel/Serial Select Pin
"L": Serial mode, "H": Parallel mode
96kHz sampling detect pin
(RX mode) "H" : fs=88.2kHz or more,
"L" fs=54kHz or Iess.
(X'tal mode) "L" : XFS96=1, "L" : XFS96=0.
Unlock & Parity Error Output Pin
"L": No error, "H": Error
Output Channel Clock Pin
Audio Serial Data Output Pin
Audio Serial Data Clock Pin
Auxiliary audio data input pin
Master Clock #2 Output Pin
Master Clock #1 Output Pin
Output Clock Select 0 Pin in parallel mode
Chip Select Pin in serial mode
Output Clock Select 1 Pin in parallel mode
Control Data Clock Pin in serial mode
Master Clock Operation Mode Pin in parallel mode
Control Date Input Pin in serial mode
Master Clock Source select Pin in parallel mode
Control Date Output Pin in serial mode
I/O
I
O
O
I/O
O
I/O
I
O
O
I
I
I
I
I
I
I
O
Note: All input pins except internal pull-down pins should not be left floating.
Description of major ICs