1-14 (No.22058)
SECTION 4
Description of major ICs
4.1
39VF0207CWHR01 (IC511) : EEPROM
• Pin layout
• Block diagram
• Pin function
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A11
A9
A8
A13
A14
A17
WE#
VDD
NC
A16
A15
A12
A7
A6
A5
A4
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
Vss
DQ2
DQ1
DQ0
A0
A1
A2
A3
X-Decoder
Address Buffer & Latches
Control Logic
Memory Address
CE#
OE#
WE#
EEPROM
Cell Array
Y-Decoder
I/O Buffers & Data Latches
DQ7~DQ0
Symbol
Pin name
Function
AMS- A0
Address Inputs
To provide memory address. During Sector-Erase AMS-A12 address lines will select the
sector.
DQ7- DQ0
Data Input/Output
To output data during read cycles and receive input data during write cycles. Data is in-
ternally latched during a write cycle. The outputs are in tri-state when OE# or CE# is high.
CE#
Chip Enable
To active the device when CE# is low.
OE#
Output Enable
To gate the data output buffers.
WE#
Write Enable
To control the write operations.
VDD
Power Supply
To provide power supply voltage: 3.0-3.6V for SST39LF512/010/020/040
2.7-3.6V for SST39VF512/010/010/040
Vss
Ground
NC
No Connection
Unconnected Pins
Summary of Contents for RX-7030VBK
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