1-16 (No.22058)
4.4
AK4112BVF-X (IC551) : Digital audio receiver
• Pin layout
• Pin function
NOTE:
All input pins except internal pull-down pins should not be
left floating.
DVDD
DVSS
TVDD
V/TX
XTI
XTO
PDN
R
AVDD
AVSS
RX1
RX2/DIF0
RX3/DIF1
RX4/DIF2
CM0/CDTO
CM1/CDT1
OCKS1/CCLK
OCKS0/CSN
MCKO1
MCKO2
DAUX
BICK
SDTO
LRCK
ERF
FS96
P/SN
AUTO
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Pin No. Symbol
I/O
Function
1
DVDD
-
Digital Power Supply Pin 3.3V
2
DVSS
-
Digital Ground Pin
3
TVDD
-
Input Buffer Power Supply Pin 3.3V or
5V
4
V
O
Validity Flag Output Pin in Parallel
Mode
TX
O
Transmit channel (through data) Out-
put Pin in Serial Mode
5
XTI
I
X'tal Input Pin
6
XTO
O
X'tal Output Pin
7
PDN
I
Power-Down Mode Pin
When "L" the AK4112B is powered-
down and reset
8
R
-
External Resistor Pin
18k
Ω
+/-1% resistor to AVSS exter-
nally.
9
AVDD
-
Analog Power Supply Pin
10
AVSS
-
Analog Ground Pin
11
RX1
I
Receiver Channel 1
This channel is selected in Parallel
Mode or default of Serial Mode.
12
RX2
I
Receiver Channel 2 in Serial Mode
12
DIF0
I
Audio Data Interface Format 0 Pin in
Parallel Mode
13
RX3
I
Receiver Channel 3 in Serial Mode
13
DIF1
I
Audio Data Interface Format 1 Pin in
Parallel Mode
14
RX4
I
Receiver Channel 4 in Serial Mode
14
DIF2
I
Audio Data Interface Format 2 Pin in
Parallel Mode
15
AUTO
O
Non-PCM Detect Pin
"L": No detect "H": Detect
16
P/S
I
Parallel/Serial Select Pin
"L": Serial Mode "H": Parallel Mode
17
FS96
O
96kHz Sampling Detect Pin
(RX Mode)
"H": fs=88.2kHz or more
"L": fs=54kHz or less.
(X'tal Mode) "H": XFS96=1
"L": XFS96=0.
18
ERF
O
Unlock & Parity Error Output Pin
"L": No Error "H": Error
19
LRCK
I/O
Output Channel Clock Pin
20
SDTO
O
Audio Serial Data Output Pin
21
BICK
I/O
Audio Serial Data Clock Pin
22
DAUX
I
Auxiliary Audio Data Input Pin
23
MCK02
O
Master Clock #2 Output Pin
24
MCK01
O
Master Clock #1 Output Pin
25
OCKS
0
I
Output Clock Select 0 Pin in Parallel
Mode
CSN
I
Chip Select Pin in Serial Mode
26
OCKS
1
I
Output Clock Select 1 Pin in Parallel
Mode
CCLK
I
Control Data Clock Pin in Serial Mode
27
CM1
I
Master Clock Operation Mode Pin0 in
Parallel Mode
CDTI
I
Control Data Input Pin in Serial Mode
28
CM0
I
Master Clock Operation Mode Pin1 in
Parallel Mode
CDTO
O
Control Data Output Pin in Serial
Mode
Pin No. Symbol
I/O
Function
Summary of Contents for RX-7030VBK
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