1-34 (No.49831)
SECTION 4
Description of major ICs
4.1
AK7740VT (IC101) : Audio DSP with AD/DA converter
• Pin layout
• Block diagram
AINL3
AINR2
AINL2
AINR1
AINL1
VREFH
AVDD
AVSS
DVSS
DVDD
XTI
XTO
36
35
34
33
32
31
30
29
28
27
26
25
AOUTL2
AOUTR2
BVSS
DVSS
DVDD
INT_RES
S_RESET
RQ
SCLK
SI
SO
RDY
1
2
3
4
5
6
7
8
9
10
11
12
CLKO
JX
SMODE
LRCLK
BITCLK
SDIN
SDINA
SDOUT
A
SDOUT
DRDY
DVSS
DVDD
48
47
46
45
44
43
42
41
40
39
38
37
AINR
3
AINL
4
AINR
4
AINL
+
AINL-
AINR
+
AINR
-
A
VSS
VCO
M
AV
D
D
AOU
T
AOU
T
13
14
15
16
17
18
19
20
21
22
23
24
48 pin LQFP
(TOP VIEW)
Note) JX , SDIN and SDINA are Pull-down pins
OUTAE
SW3
SW0
SDATA
SW2
SDATA
AOUTL
VREFF
AINL-
AINL-
AOUTR
SDOUTA
SDINA
SDINA
SDIN
SDIN
ISEL[2:0]
SDOUTD1
SDOUTD1
SDOUT
SDOUT
72kbit DLRAM
DAC1
CONTROLLER
ADC
SW2
SW1
C
Q
A
B
SDATA
AOUTL
AOUTR
AOUTL1
VCOM
VREFF
AOUTR1
AOUTL2
AOUTR2
DAC2
*SW1,SW2,SW3,ISEL[2:0],
OUTAE control register
INT_RESET
INT_RESET
SMODE
XTO
XTI
CLKOUT
BITCLK
LRCLK
SMODE
XTO
XTI
CLKOUT
BITCLK
LRCLK
S_RESET
S_RESET
AINL+
AINL+
AINL1
AINL2
AINL3
AINL4
AINR1
AINR2
AINR3
AINR4
AINR-
AINR-
AINR+
AINR+
Note)
When C is "L" (0) then A connects with Q
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