(No.YF139)2-19
2-20(No.YF139)
GA_SI
MCLKI
TG_HD
HDCCD
GA_SEN
MCLKI
TG_HD
VDCCD
GA_SCK
GA_SCK
VDCCD
HDCCD
GA_SI
SSGFLD
GA_SEN
VDCPU
SSGFLD
VDCPU
FLDCPU
FLDCPU
TG_VD
TG_VD
HDIRS
R4412 1k
VDIRS
R4413
1k
C4402
0.1
GND
REG_3.1V
MCLKI
R4414
1k
L4401
NQR0129-002X
TG_VD
TG_HD
C4401
4.7
VDCCD
R4405
1k
FLDCPU
HDCCD
SSGFLD
VDCPU
R4406
1k
CAM_VD
AFE_RST
GA_SCK
R4402 100
GA_SEN
GA_SI
R4403 100
IC4401
JCY0228
1
CLR
2
NC
3
NC
4
NC
5
FLDCPU
6
GND
7
NC
8
NC
9
VDCPU
10
NC
11
NC
12
ENCFLD
13
HDCCD
14
NC
15
NC
16
NC
17
VDCCD
18
NC
19
NC
20
SCK
21
NC
22
SEN
23
NC
24
SDT
25
VDMDA
26
NC
27
VDIRS
28
NC
29
HDIRS
30
VDD
31
NC
32
SMC
33
TDI(SIN)
34
TDD(SOUT)
35
TMS
36
TCK
37 TRST
38 NC
39 NC
40 NC
41 VDTG
42 NC
43 NC
44 HDTG
45 NC
46 NC
47 NC
48 MCLKI
R4410 1k
R4411 1k
C4403 0.1
R4401 0
4403
L
R
VACANT NO.
LAST NO.
4404,4407,4408,4409
4414
4401
4401
C
IC
MAIN(GA)
1
0
yf139_y30346001a_rev1.2
TO OP DRV
TO P.PRCS,OP DRV
TO P.PRCS
TO DSP,P.PRCS
TO DSP,P.PRCS
TO MAIN IF(CN105),
P.PRCS
TO SUB CPU,P.PRCS
MAIN(GA) SCHEMATIC DIAGRAM
NOTES: 1. For the destination of each signal and further line connections that are cut off from this diagram, refer to "BOARD INTERCONNECTIONS".
2. The parts with marked ( ) is not used.
