(No.YF139)2-13
2-14(No.YF139)
VI7
VI5
VI2
VI3
VI6
VI4
VI0
VI1
C3211
1
OSD_VD
VI6
C3207
0.01
VI3
0.1
C3217
R7859
36k
L3201
NQR0129-002X
R3213
12k
R3221
Short
R3206
R3209
R7813
620
C3215
OPEN
R3701
R7802
8.2k
R7808
620
MPGFLD
C3205
0.1
R3207
R3204
VI0
GND
R7851
33k
R7801
33k
Q3201
OPEN
2
6
3
5
4
1
R3208
100
L7851
TL3203
DV2OUT2
VDCVF
R3214
2.7k
C3203
0.01
R3702
R7853
36k
C3230
OPEN
C7801
4.7/16
R3201
C3213
OPEN
C3220
4.7
Y_OUT
L3203
NQR0129-002X
C3208
1
R3211
C7803
1
R7815
12k
C3705
0.01
VI7
D3701
UMZ6.8EN-W
1
2
3
4
5
MON_G
IC3202
MB90099PFV139EX
20
HD
19
VD
18
VC0
17
VC1
16
VC2
15
BLKA
14
VC3
13
BLKB
12
TSTO
11
BLKC
10 GND
9 TEST
8 EXD
7 NC
6 SDR
5 VDD
4 RST
3 SIN
2 CS
1 SCLK
DV2OUT4
C3206
0.1
VI4
C3201
0.01
T
C3701
10/6.3
R3210
HRP
C3225
1
IC3701
BH7612FV-X
16
GND
15
VCC
14
13
PSCTRL
12
GND
11
10
9
PVCC
1
2
GND
3
4
5
6
7
8
PGND
DV2CKOUT
C3212
SHORT
C3702
0.1
C7806
1/16
R3212
18k
C3204
0.01
PSCTL
C3703
1
RA3202
10
1
2
3
4
8
7
6
5
SREG2.5V
Q7801
UMX1N-W
2
1
4
5
3
6
MON_R
ANA_CS
R3220
R3216
820
R7817
6.8k
VI2
C3227
1
DV2OUT7
R7814
2.2k
Q7803
UMX1N-W
2
1
4
5
3
6
ANA_OUT
MPGVSYNC
R3219
OPEN
L7801
REG_3.1V
C3224
1
TL3202
MON_B
C3216
0.1
C3704
0.01
L3206
0
R7804
2.2k
HDCVF
C7802
1/16
C3202
0.01
DV2OUT1
VI5
C7804
1/16
DV2OUT5
MPGHSYNC
DV2OUT3
L3701
R3709
1.2k
R7803
620
TL3201
R7854
33k
DV2OUT6
C3214
OPEN
R3703
68
R7810
12k
Q7802
UMX1N-W
2
1
4
5
3
6
ANA_IN
REG_14V
R3710
2.2k
R3215
2.7k
RA3201
10
1
2
3
4
8
7
6
5
R3218
OPEN
R7805
12k
C7805
1/16
R7809
2.2k
ANA_CLK
R7856
36k
C_OUT
C7852
OPEN
IC3204
R1100D251C-X
1
VOUT
2
VDD
3
GND
R3708
10k
OSD_CS
ANA_RST
R3217
820
R7812
6.8k
R3203
C3218
0.01
VI1
R3222
Short
R7857
33k
Q3701
BC847PN-X
5
4
6
2
1
3
DSP_RST
C3210
0.1
C3209
0.1
R7807
8.2k
DV2OUT0
REG_4.9V
IC3201
JCP8075
1
NC1
2
NC1
13 NC1
14 NC1
54 VSS
3
RST
97 CSO0
55 CSO1
133 CSO2
99 CSO3
4
YSO0
98 YSO1
134 YSO2
56 YSO3
5
VDD(I/O)
100 OUTH
135 OUTV
6
OUTH2
57 OUTV2
101 ZCNT
7
SDOUT
58 VDD(CORE)
102 VSS
136 CLK
8
SDIN
59 SCLK
103 CS
9
VC0
60 VC1
137 VC2
104 VC3
10 BLK1
61 BLK2
138 BLK3
11 HDOUT
62 VDOUT
105 CLKOSD
139 HDCVF
12 VDCVF
63 VSS
161 NC2
162 NC2
163 NC2
164 NC2
165 NC2
15
NC1
26
NC1
27
NC1
28
NC1
106
VDD(I/O)
107
CSYNC
140
SCANMODE
65
SCANEN
16
ADDATEST
141
VCC
66
IPTEST
17
VDD(I/O)
108
HRP1
67
HRP2
18
VDD(CORE)
142
WYSI0
109
WYSI1
19
WYSI2
68
WYSI3
143
MONI1
110
MONI2
20
VDD(CORE)
69
VSS
144
WCLK
21
WCSI0
70
WCSI1
111
WCSI2
71
WCSI3
22
WINV
112
WINH
145
SDR_ONH
23
VDD(I/O)
146
VSS
72
VDD(CORE)
25
RESVD
24
RESHD
73
AMUTE
113
SCANI1
114
SCANI2
74
VSS
166
NC2
167
NC2
168
NC2
169
NC2
170
NC2
39
NC2
40
NC1
41
NC1
52
NC1
76
VDD(CORE)
29
SCANI3
30
VSS(8DA)
115
VDD(8DA)
147
COUT
116
VREF2
77
CBOUT
148
COMP2
117
ABAR2
78
CROUT
31
IREF2
149
VDD(8DA)
118
VSS(8DA)
79
NC
32
NC
150
NC
119
NC
33
VDD(10DA)
80
VSS(10DA)
151
VREF1
81
YSOUT
34
COMP1
120
ABAR1
152
YCOUT
35
IREF1
82
CLPY
121
VYIN
83
VSS(8AD)
36
VDD(8AD)
122
VRM
153
VRL
37
VRH
84
CIN
123
VDD(8AD)
38
VSS(8AD)
85
VSS
171
NC2
172
NC2
173
NC2
174
NC2
175
NC2
53
NC1
64
NC1
75
NC1
86
NC1
154
VCCQ
87
CSI0
42
CSI1
124
VSSQ
125
CSI2
88
CSI3
155
VCCQ
43
VDD(I/O)
126
CSI4
89
VSS
44
VDD(CORE)
127
CSI5
156
VSSQ
90
CSI6
45
CSI7
128
INH
91
INV
46
VDD(CORE)
157
VSS
129
VDD(I/O)
158
VCC
47
VSS
92
YSI0
48
VDD(CORE)
93
YSI1
130
VSSQ
49
YSI2
94
YSI3
131
VCCQ
50
YSI4
95
YSI5
159
VSSQ
132
YSI6
51
YSI7
96
VDD(I/O)
160
VCCQ
176
NC2
177
NC2
178
NC2
179
NC2
180
NC2
ASPECT
V_OUT
C3219
0.1
T
C3709
100/4
T
C3708
22/4
T
C3707
22/4
T
C3706
100/4
TL3204
R3202
R3205
Q3202
2SC4617/QR/-X
R3223
R3224
(1608)
SREG1.8V
R3225
open
_0.5%
_0.5%
0
Ω
0
Ω
_0.5%
0
Ω
_0.5%
0
Ω
0
Ω
_0.5%
0
Ω
_0.5%
0
Ω
_0.5%
0
Ω
0
Ω
_0.5%
0
Ω
_0.5%
0
Ω
_0.5%
_0.5%
22
µ
_0.5%
10
µ
_0.5%
_0.5%
_0.5%
_0.5%
_0.5%
_0.5%
_0.5%
_0.5%
_0.5%
0
Ω
_0.5%
0
Ω
0
Ω
100
33
(L:OUTV,OUTH=HiZ)
BPF
7dB
1.8k
20k
LPF
6dB
200k
7dB
COMP
7dB
L
3221~3223,3226,3228,3229
Q
R
SYMBOL NO. 7801~
7801
7851
VACANT NO.
L
IC
7852,7855,7858
R
3230
7806
Q
3202
C
7859
7817
LAST NO.
3202,3204,3205
C
SYMBOL NO. 7851~
VACANT NO.
LAST NO.
RA
R
VACANT NO.
3202
7803
LAST NO.
L
7851
7852
3203
3225
SYMBOL NO. 3201~
3206
3204
C
3202
D
7806,7811,7816
MAIN(V I/O)
1
0
yf139_y10622001a_rev0.1
TO DSP
TO MPEG2,
DSP
TO MPEG2
TO SUB CPU
TO MAIN IF(CN101),
SUB CPU,AUDIO
TO SUB CPU
TO OP DRV
TO MAIN IF
TO MPEG2,
DSP MEM
TO USB HOST
TO SUB CPU,
DSP
TO MAIN IF
(CN101)
TO MAIN IF
(CN101)
TO MAIN IF
(CN101,110)
MAIN(V I/O) SCHEMATIC DIAGRAM
NOTES: 1. For the destination of each signal and further line connections that are cut off from this diagram, refer to "BOARD INTERCONNECTIONS".
2. The parts with marked ( ) is not used.
