JVC GZ-MG67AA, Service Manual

Page: 42 / 82

(No.YF139)2-7 2-8(No.YF139)
ACESLED
ZOOMSW
SCPU_SI
SCPU_SI
REG_CS
FLSH_RST
SYSSEL1
AUDIO_CS
ZEROG_H
EEPRM_DI
OSD_CS
3AAZEROG
ANA_CLK
KEY_BCH
AVREF_OF
CHRG_EVR
UNREGCHK
V27_OUT
SBT5
A_MUTE
PD_L
KEY_ACH
PMEDIA
DIAL_OFF
ANA_IN
ADP_L
SCPU_SO
T_BATT
SYSSEL0
ADP_L
CHRGLED
DIAL_REC
TVSEL
KEY_CCH
ANA_OUT
ANA_OUT
ANA_CLK
MONI_SW
HOSTLED
BATT_H
AUDIO_CS
I_MTR
SCPU_CS
KEY_BCH
DIAL_REC
3AAZEROG
I_MTR
KEY_ACH
CHRG_EVR
DIAL_PB
MONI_SW
ZOOMSW
PDET
SCPU_CS
DC_CHEK
DIAL_OFF PMEDIA
SBD5
UNREGCHK
OSD_CS
SYSSEL0
AVREF_OF
ANA_OUT
DIAL_PB
A_MUTE
V27_OUT
IR_RMC
V_BATT
SCPU_SCK
FLSH_RST
PSCTL
ANA_CLK
SYSSEL1
EEPRM_DI
EEPRM_CS
LCDRVS
CHRGLED
SDET
SDET
ZGH_THRU
LCDRVS
ANA_RST
SETSW
KEY_CCH
LCD_CTL
EEPRM_CS ANA_CLK
EEPRM_DO
LCD_CTL
ACESLED
ZGH_THRU
ANA_CS
SCPU_SO
INFOSW
SETSW
V_BATT
PD_L
LCD_CS
L_MUTE
REG_CS
TVSEL
HOSTLED
IR_RMC
TG2_RST
EEPRM_CK
T_BATT
EEPRM_DO
PDET
SBD5
PS_ZEROG
ZGH_OUT
T_BATT
DBATT
EEPRM_CK
SCPU_SCK
ANA_OUT
ANA_IN
L_MUTE
PSCTL
ZGH_OUT
PS_ZEROG
DC_CHEK
ANA_RST
ANA_CS
DBATT
INFOSW
TG2_RST
BATT_H
SBT5
LCD_CS
ISO200
ISO100
ISO100
ISO200
R1074 10k
R1020 1K
OSD_CS
TL1066
SJIG_RX
SCPU_CS
C1020
0.01
C1016
0.01
BUZZER
C1025
0.1
EEPRM_CK
R1008 1K
ANA_OUT
R1010
680
REC_SW
C1004
0.1
L1002
10u
KEY_A
DATA_OUT
R1005
2.2K
R1022 1k
SCPU_SO
ANA_CS
Q1001
DTC124EE-X
R1073 62k
ANA_RST
R1054
47k
SBD5
C1046 0.1
IC1001
MN102H60GJD
91
LCD_BL
89
S_DET
31
DIAL_PB
32
DIAL_OFF DIAL_REC
30 5
CHRG_EVR
35
DC_CHEK
42
MODE_SW/P_MEDIA
12
WORD
82
RESET
19
VSS
20
XI
21
XO
24
OSCO
23
OSCI
40
AUDIO_CS
86
A_MUTE
87
ISO100
85
L_MUTE
4
FAN_CTL2
41
PD_L
3
HOSTLED
75 NMI
76 JLIP_INT
38 INFO_SW
33 LCD_OPEN
80 BATT_H
36 ADP_L
78 OSD_VD
77 ZEROZINT
53 3AAZEROG
83 VDD
58 REMOTE
60 ACESLED
81 CHRGLED
26 ZEROG_H
29 DSP_RST
16 AFE_RST
48 NT_PAL
96 RTC_INT
65 V_BATT
44 T_BATT
62
UNREGCHK
47 ZOOM_SW
63 KEY_A
64 KEY_B
46 KEY_C
45 I_MTR
54
VREF+
43
VREF-
34
AVDD
66
VDD
61
AVSS
57
SET_SW
59
V27_OUT
7
RESERVED
8
RESERVED
11
ZDH_THRU
37
RESERVED
18
RESERVED
98
AVREF_OF
99
PS_ZEROG
100
ZGH_OUT
25
MODE
92
VSS
73
SBD5
74
SBT5
88
P_DET
95
D_BATT
49
ISO200
27
FLSH_RST
71
ANA_IN
72
ANA_OUT
70
ANA_CLK
55
RXD
56
TXD
97 EEP_CS
51 SCPU_IN
52 SCPU_OUT
50 SCPU_CLK
68 DATA_IN
69 DATA_OUT
67 CLK_OUT
79 SCPU_CS
22 VDD
28 RTC_CS
1 REG_CS
39 OSD_CS
14 EEP_IN
15 EEP_OUT
13 EEP_CLK
9 ANA_CS
93 BZ_FREQ
94 BZ_ENV
90 ANA_RST
10 SYTG_RST
2 LCD_CS
17 VDD
6 LCD_RVS
84 PS_CTL
R1069
100k
R1057
100k
R1001
100k
SCPU_SI
ANA_CLK
REG_CS
CHRG_LED
R1007
4.7k
R1009
680
R1077
1M
R1086 0R0
TL1005
LCD_CTL
IC1002
RS5C314-X
8
VDD
7 XIN
6
XOUT
5
INTR
4 VSS
3 SIO
2 CLK
1 CS
R1072 82k
R1055
10k
A_MUTE
TL1067
C1026
0.1
CLK_OUT
ADP_L
R1006
4.7k
PD_L
SJIG_TX
C1006
7p
R1043
100k
PS_ZEROG
R1058
100k
SET_SW
V_BATT
ANA_CLK
D_BATT
R1056
4.7k
SJIG_RST
ANA_CLK
PLAY_SW
R1028 1k
3AAZEROG
L_MUTE
GND
ZOOM_SW
R1051 2.7k
R1062
100k
D1001
DA221-X
2
1
3
R1036 OPEN
P_MEDIA
R1065
1k
Q1002
2SC4617/QR/-X
SCPU_SCK
C1043
0.01
R1024 1k
ANA_IN
TL1004
R1083
100k
C1017
0.01
REG_3.1V
T_BATT
R1017 1k
C1018
0.01
X1002
NAX0564-001X
PSCTL
IC1005
SN74AHC1G04DC-X
123
4
5
P_DET
S_DET
D1002
1SS376-X
LCD_CS
IC1007
TC75S56FU-X
1
[-]
2
VSS
3
[+]
4
OUT
5
VDD
INFO_SW
Q1003
DTA124EE-X
R1052 18k
R1018 1k
R1053
150k
UNREGCHK
KEY_B
ZEROG_H
POFF_SW
IC1004
SN74AHC1G08DC-X
74AHC1G08GW-X
1
2
3 45
R1066 1k
T
C1005
10/6.3
C1001
0.1
Q1004
2SC5658/QRS/-X
EEPRM_CS
C1015
0.01
TG2_RST
CHRG_EVR
C1031
1
R1014
OPEN
ZGH_THRU
ACES_LED
C1008
0.01
R1075 100k
C1034
0.01
C1044
0.01
R1031 1k
DC_CHEK
LCD_RVS
R1085
0R0
R1016
2.2k
C1013
0.01
KEY_C
L1001
NQR0129-002x
R1045
1k
C1045
0.01
R1061
100k
V27_OUT
R1060
100k
R1003
2.2K
OSD_VD
D1003
OPEN
R1070
100k
SBT5
FLSH_RST
LIT_3V
WORD
ANA_OUT
AUDIO_CS
ANA_OUT
AL_3.1V
R1023 1k
TL1032
R1071
100k
C1014
0.01
EEPRM_DO
LCD_OPEN
R1015
OPEN
R1059
100k
R1068 100k
IR_RMC
R1037
1k
AFE_RST
R1063 47k
HOST_LED
R1025 1k
Q1006
DTA124EE-X
R1019 1k
TL1030
R1004
2.2K
Q1005
2SJ347-X
D 1
G
2
S 3
R1076 100k
X1001
NAX0784-001X
1 2 3
R1046
OPEN
R1084
0R0
IC1003
S-80827CNNB-G-W
1
OUT
2
DET
3 4
VSS
R1082
100k
R1064 1k
R1030 1k
EEPRM_DI
ZGH_OUT
I_MTR
TVSEL
DSP_RST
R1029 1k
ISO100
ISO200
yf139_y10621001a_rev0.1
MAIN(SUB CPU) 1 0
TO MAIN IF(CN101)
TO MAIN IF(CN103)
TO MAIN IF(CN110)
TO MAIN IF(CN101,
103,110)
TO MAIN IF(CN110)
TO MAIN IF(CN103)
TO MAIN IF(CN101),
AUDIO,V I/O
TO MAIN IF(CN101),
AUDIO,V I/O
TO MAIN IF(CN101)
TO AUDIO
TO MAIN IF(CN101)
TO MAIN IF(CN121)
TO MAIN IF(CN101)
TO MAIN IF(CN104)
TO MAIN IF(CN101)
TO MAIN IF(CN103)
TO MAIN IF(CN101)
TO MAIN IF(IC171)
TO MAIN IF(CN101,
103,110,IC121)
TO MAIN IF(CN103)
TO P.PRCS
TO GA,P.PRCS
TO P,PRCS
TO MAIN IF(CN105)
TO DSP MEM
TO DSP
TO V I/O,DSP
TO V I/O
TO V I/O
TO V I/O
TO V I/O
TO V I/O
MAIN(SUB CPU) SCHEMATIC DIAGRAM
NOTES: 1. For the destination of each signal and further line connections that are cut off from this diagram, refer to "BOARD INTERCONNECTIONS".
2. The parts with marked ( ) is not used.