(No.YF087)2-31
2-32(No.YF087)
CN501
CN901
AV JACK
BATTERY TERM
DC JACK
MMC_DOUT
GND
D_BATT
GND
REG_3.1V
MMC_CD
AU_SIG/L
ADP_DC
GND
MMC_CS
SD_WP
AU_SIG/R
ADP_DC
GND
GND
GND
ADP_DC
BATT_+
BATT_+
BATT_+
BATT_+
MMC_CLK
GND
ADP_DC
GND
T_BATT
GND
QGF0528F1-40X
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
BATT_+
BATT_+
ADP_L
GND
GND
BATT_+
ADP_DC
V_OUT
REG_3.1V
MMC_DIN
ADP_DC
P_DET
R905
10k
D901
OPEN
1
2
3
R907
R902
10k
11
CARD_DET
12
VSS(GND)
13
SD_WP
R906
10k
C901
0.01
R904
10k
R903
10k
14
GND
10
GND
R901
10k
L901
NQR0006-001X
NNZ0104-001X
9
SD_DATA2
1
MMC_CS
2
Dat2MMC
3
VSS(GND)
4
VDD(DSC_3V)
5
MMC_CLK
6
VSS2/CD
7
Dat2Host
8
SD_DATA1
T
C902
10/6.3
C903
OPEN
GND
SD_WP
MMC_DIN
MMC_DOUT
MMC_CD
MMC_CLK
REG_3.1V
MMC_CS
D503
UDZS6.8B-X
L501
NQR0251-004X
C501
0.01
L503
NQR0251-004X
C503
OPEN
J502
QNS0078-001
1
2
3
5
4
7
R501
100
C504
OPEN
C502
0.01
L502
NQR0251-004X
R502
100
AU_SIG/R
P_DET
V_OUT
AU_SIG/L
GND
TP2
[T]
TP3
[D]
TP1
[+]
TP4
[-]
J501
QNA0039-001
4
5
3
6
2
ADP_L
GND
ADP_DC
BATT_+
T_BATT
GND
D_BATT
BATT_+
D502
MA8068-X
D501
EMZ6.8N-X
1
2
3
C505
OPEN
D504
MA8068-X
C506
OPEN
BATT_CHK
BATT_CHK
L901
CN901
R901-R907
with DSC
C901,C902
without DSC
0
Ω
y30311001a_rev0.1
REAR
5
0
TO SD
TO MAIN IF(CN103)
REAR SCHEMATIC DIAGRAM
NOTES: 1. For the destination of each signal and further line connections that are cut off from this diagram, refer to "BOARD INTERCONNECTIONS".
2. The parts with marked ( ) is not used.