Juniper LN1000-V, Hardware Manual

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2.
Lift the injector/ejector latch on the right side of the router front panel to disengage
the connector on the router from the backplane connector.
3.
Slide the router out of the guide rails.
Related Topics LN1000–V Mobile Secure Router Description on page 3
•
Powering On the LN1000–V Mobile Secure Router
The LN1000-V router derives its power from the chassis in which it is installed; it
automatically powers on when inserted into the connector in the VITA 46.0-compliant
chassis.
Monitor router startup on the console and the LED on the front panel of the LN1000-V
router to verify that the router is booting properly.
As a standard part of the boot process, the router runs startup power-on self test (SPOST)
and then power-on self test (POST) diagnostics. A successful startup looks similar to
the following example:
CPU Memory (Data32: 00000000-0007ffff) test completed, 1 pass, 0 errors
CPU Memory (Data32: 0f000000-0fffffff) test completed, 1 pass, 0 errors
CPU Memory (Addr32: 00000000-0007ffff) test completed, 1 pass, 0 errors
CPU Memory (Addr32: 0f000000-0fffffff) test completed, 1 pass, 0 errors
Boot Flash: 16 MB in 131 Sectors (portwidth: 16bit chipwidth: 16bit)
OCTEON CN56XX pass 2.0, Core clock: 600 MHz, DDR clock: 266 MHz
Initializing USB
Device 1:
Product DOTG Root Hub
Device 2:
Manufacturer
Product USB Flash Memory
SerialNumber 00147808E485C92043770566
Initializing IDE
Initializing FPGA
Programming /cf/usr/share/pfe/firmware/563-029572.bit: 2067590 bytes
Programmed successfully (time: 883475051 ticks)
Checking for init_data
No init_data
PCIe: Waiting for port 0 link
PCIe: Port 0 link active, 1 lanes
Probing PCIe port 0
0:00:00.0 0x003b1304
PCIe port 0 had 1 busses
HWA FPGA Version 0x0004090900000013
PCIe: Waiting for port 1 link
PCIe: Port 1 link active, 4 lanes
Probing PCIe port 1
1:00:00.0 0x0009184e
PCIe port 1 had 1 busses
IDP Revision Date-Time: 05/28/08-18:00:00
11 Copyright © 2010, Juniper Networks, Inc.
Chapter 3: Installing the LN1000-V Mobile Secure Router