SP-5000M-CXP4 / SP-5000C-CXP4
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6.3.2 Vertical timing
Sensor Pixel Format: 8-bit
Output format: 1X–1Y, CXP-6_2
Trigger Mode: ON, Exposure Mode: Timed
1L: 165 clocks, 1 clock: 11.574 ns
6.3.2.1 Vertical Binning OFF
Fig.15 Vertical Timing (Vertical binning OFF)
6.3.2.2 Vertical Binning ON
Fig. 16 Vertical timing (Vertical binning ON)
FVAL
DVAL
CMOS
Exposure
Video
Exposure
Active
Frame
Active
2048L
12 ~13L(Min)
8 ~9L
FVAL
DVAL
CMOS
Exposure
Video
Exposure
Active
Frame
Active
1024L
12 ~13L(Min)
8 ~9L