SP-5000M-CXP4 / SP-5000C-CXP4
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5.3.7.1 Basic block diagram
Note1: The pixel clock is 86.4 MHz.
Note2: Items written in blue are available only if Type 3 is selected for AUX connector.
Fig. 6 GPIO
Soft Trigger
FVAL IN
Exposure Active
Acquisition Trigger Wait
Acquisition Active
Frame Trigger Wait
Frame Active
GPIO 4 (TTL IN 1)
GPIO 7 (CXP IN)
GPIO 10 (TTL IN2)
GPIO 11 (LVDS IN)
Pixel Clock
Cross Point
Switch
12 bit Counter
INV
INV
INV N
NAND
INV
Non INV
Pulse Generator
20 bit counter x 4
CLR
Sel Bit (5,0)
Sel Bit (7)
Sel Bit (7)
Pulse Generator 0
Pulse Generator 1
Pulse Generator 2
Pulse Generator 3
Trigger 2 (Frame Start)
GPIO 1 (TTL OUT 1)
GPIO 8 (TTL OUT 2)
GPIO 9 (TTL OUT 3)
Sel Bit (7)
Clock IN
Clear IN
Gate 1
Gate 2
User output 0
User output 1
User output 2
User output 3
GPIO 5 (OPTO IN 1)
Trigger 1 (Acquisition Stop)
Trigger 0 (Acquisition Start)
GPIO 2 (Opt OUT )