32
ADwin-Gold
Hardware Manual, Version 2.3
ADwin
9. CO1 Counter Add-On
9.1 Hardware
The counter add-on CO1 has
four 32 bit counters
, which you can configure
and read out individually or all 4 together by software (the block diagram below
shows the design of a single counter).
The counters can be
internally or externally clocked
and are read out via
accompanying latches. All counters have each a latch register A, the counters
1 and 2 have additionally a latch B.
The counter values can be cleared or transferred in a latch by using program-
ming commands or (at special configurations) when there is an external signal
at CLR/LATCH.
There are the following operating modes: event counting (external clock) and
pulse width measurement (internal clock); see also chapter 9.3/9.4:
1.
Event counting
: Incrementing/decrementing of the counter is caused by
external square-wave signals at the inputs A/CLK and B/DIR. A signal at
CLR/LATCH has the effect that either the counter is set to zero (CLR) or that
the counter values are written into the latch (LATCH).
There are the modes:
–
Clock and direction
: Every positive edge at CLK increments or
decrements the counter values by one. The signal at DIR determines the
counting direction (0 = count down; 1 = count up).
–
Four edge evaluation
: Every edge of the signals (phase-shifted by 90
degrees) at A/CLK and B/DIR causes the counter to increment/decrement.
The counting direction is determined by the sequence of the rising/falling
edges of these signals. This mode is particularly used for quadrature
encoders.
2.
Pulse width measurement
: Incrementing/decrementing of the counter is
caused by an internal reference clock generator with a signal frequency of
20 MHz (optionally 5 MHz after scaler). The square-wave signal at CLR/
LATCH is evaluated: With every positive edge the counter values are written
to latch A, with a negative edge to latch B.
You can calculate:
– the period duration of the input signal at CLR/LATCH from the values in
latch A or latch B.
–
the impulse width and pause time from the values in latch A and latch B
(only counters 1 and 2).
Counter
Latch register
External clock input
Internal clock input
NOTE:
Only Counter #1 is shown for clarity of the schematic. The 20 MHz clock signal is distributed to all dividers/counters.
G
20 MHz
Control-Registers
32 bit Latch B (#1& #2 only)
32 bit Counter (#1...#4)
32 bit Latch A (#1...#4)
CLK
EN
CLR
A / CLK
ADwin-GOLD
bus
Data
Data
Data
B / DIR
CLR /
LATCH
DIR
DIR
CNT_INPUTMODE
CNT_SET
(CNT_MODE)
CNT_CLEAR
CNT_LATCH
CNT_SET
(CNT_MODE)
CNT_MODE
Up
4-edge-
evaluation
ref.-CLK
4k7
4k7
4k7
to f
ref
-switch of
other counters
Divider
÷ 4
9. CO1 Counter Add-On
