29
Chapter 4
BIOS Setup
DRAM Timing Select
The first chipset settings deal with C P U access to dynam ic
random access m em ory (D R AM). The default tim ings have been
carefully chosen and should only be altered if data is being lost.
Such a scenario m ight well occur if your system had m ixed
speed D R AM chips installed. Longer delays m ight result,
however this preserves the integrity of the data held in the slower
m em ory chips.
SDR DRAM CAS Select
Select the number of clock cycles of CAS latency depends on
the DRAM timing .
[2,3 (
Default Value)
]
Refresh Queue
Select the depth value of the DRAM refresh queue.
[Disabled,Depth 2,Depth 4,Depth 8
(Default Value)
]
DRAM Perform ance
Select the performance parameter of the installed DRAM. Do not
reset this field from the default value by the system designer
unless you install new memory that has a different performance
rating than the original DRAMs.
[Failsafe,slow, Normal
(Default Value)
Fast,Ultra,Ultra2]
Enhance Page M ode Tim er
Select the preset value of the Page Life Timer counter . When
disabled , the open pages mode will not be closed even the PLT
counter expired .
[16clk,32clk,
(Default Value)
64clk,128clk,Disabled]
Refresh Rate
Select the rating for DRAM refresh control.
[Normal
(Default Value),15.6us,7.8us
]
AT bus Clock
Select the speed of the AT bus in term s of a fraction of the C P U
clock speed , or at the fixed speed of 7.16 MH z.
[7.16MH z,C LK2/2,C LK2/3,C LK2/4
(Default Value)
,C LK2/5,C LK2/6]
System BIOS Cacheable
Setting to
enabled, accesses to the system BIOS will be cached.
[E nable
(Default Value)
, D isabled]
