37
3.5 CHIPSET FEATURES SETUP
This setup page is used to specify advanced features available through the chipset. The default
settings have been chosen carefully for the most operating conditions. DO NOT change the
value of any field in this setup page without full understanding.
3.5.1 SDRAM RAS-to-CAS Delay
This field specifies the length of the delay inserted between the RAS and CAS signals of the
DRAM system memory access cycle if SDRAM is installed. The settings
Options
2 / 3 (*)
3.5.2 SDRAM RAS Precharge TIME
This field specifies the length of the RAS part of the DRAM system memory access cycle when
Synchronous DRAM system memory is installed in the computer.
Options
2 / 3 (*)
3.5.3 SDRAM CAS latency TIME
You con select CAS latency time in HCLKs of 2 or 3. The system board designer should set the
values in this field, depending on the DRAM installed.
Options
2 / 3(*)
3.5.4 SDRAM Precharge Control
This field specifies the length of the RAS part of the DRAM system memory access cycle when
Synchronous DRAM system memory is installed in the computer.
Options
Enabled / Disabled (*)
3.5.5 DRAM Data Integrity Mode
When enabled, the BIOS will use ECC (Error Checking and Correcting) protocol to increase
integrity of system data. When ECC is selected, all memory modules the system used must support
ECC.
Options
ECC / Non-ECC (*)
3.5.6 System BIOS Cacheable
When enabled, accesses to the system BIOS will be cached.
Options
Enabled (*) / Disabled
3.5.7 Video BIOS Cacheable
When enabled, access to the video BIOS will be cached.
Options
Enabled / Disabled (*)
