iWave iW-RainboW-G27M Hardware User'S Manual Download Page 51

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i.MX8 SMARC SOM Hardware User Guide

iWave Systems Technologies Pvt. Ltd.

2.9

Other Features

2.9.1

Fan Header

The i.MX8 SMARC SOM supports a Fan Header to connect cooling Fan if required. This Fan Header (J2) is physically

located at the top of the board as shown below.

Figure 6: Fan Header

Number of Pins

- 2

Connector Part

- 0530480210 from Molex

Mating Connector

- 51021-0200 from Molex

Compatible FAN (Example) - 109P0405J602 from Sanyo Denki America Inc.

Table 5: FAN Header Pin Assignment

Pin No

Signal Name

Signal Type/
Termination

Description

VCC_5V

O, Power

+5V Power output to FAN.

GND

Power

Ground.

Fan Header (J2)

Summary of Contents for iW-RainboW-G27M

Page 1: ...REL1 0 Page 1 of 71 i MX8 SMARC SOM Hardware User Guide iWave Systems Technologies Pvt Ltd iW RainboW G27M i MX8 QuadMax QuadPlus SMARC System On Module Hardware User Guide...

Page 2: ...s proprietary material for the sole use of the intended recipient s Do not read this document if you are not the intended recipient Any review use distribution or disclosure by others is strictly proh...

Page 3: ...ata and associated issues Trademarks All registered trademarks product names mentioned in this publication are the property of their respective owners and used for identification purposes only Certifi...

Page 4: ...Flash Optional 16 2 6 Network Communiation 17 2 6 1 Wi Fi and Bluetooth Interface 17 2 7 SMARC PCB Edge Connector 18 2 7 1 Gigabit Ethernet 23 2 7 2 SERDES and MDIO Interface Optional 25 2 7 3 SD Inte...

Page 5: ...10 i MX8 Pin Multiplexing on SMARC Edge 54 2 11 i MX8 Pin Multiplexing on Expansion Connector 60 3 TECHNICAL SPECIFICATION 63 3 1 Electrical Characteristics 63 3 1 1 Power Input Sequencing 63 3 1 2 Po...

Page 6: ...on of Heat Spreader 66 Figure 11 Mechanical dimensions of i MX8 SMARC SOM 68 Figure 12 i MX8 SMARC SOM Development Platform 70 List of Tables Table 1 Acronyms Abbreviations 7 Table 2 Terminology 9 Tab...

Page 7: ...display transmitter are concentrated on the Module The Modules are used with application specific Carrier Boards that implement other features such as audio CODECs touch controllers wireless devices...

Page 8: ...p LPDDR4 Low Power Double Data Rate4 MHz Mega Hertz MIPI Mobile Industry Processor Interface MLB Media Local Bus OTG On The Go PCB Printed Circuit Board PCIe Peripheral Component Interconnect express...

Page 9: ...erential Signal GBE Gigabit Ethernet Signal PCIe PCIe differential pair signals SATA Serial Advanced Technology Attachment differential pair signals USB HS Universal Serial Bus High Speed differential...

Page 10: ...ed functionality then the signal name is mentioned as functionality name Functionality Name Example ENET1_RGMII_TXC In this signal ENET1_RGMII_TXC pad is used for same functionality If CPU pin selecte...

Page 11: ...x 1 UART x 2 SCU_UART0 M41 UART43 20pin Header Optional JTAG SJC SPDIF DMA_I2C2 x 1 SPDIF DMA_I2C2 Wi Fi BT Module UART12 UART HDMI TX5 HDMI x 1 DP x 1 LVDS1_CH0 LVDS1_CH14 MIPI DSI0 MIPI DSI14 MIPI D...

Page 12: ...Flash Optional Other On SOM Features WiFi 802 11a b g n ac BT 5 0 Module5 6 Gigabit Ethernet PHY Transceiver x 2 USB 3 0 High Speed 4 Port Hub FAN Header Debug UART JTAG Header Optional SMARC PCB Edg...

Page 13: ...GB LPDDR4 chips If 8GB 64Gb LPDDR4 chips are available then 16GB RAM can be supported on Board 3 Memory Size will differ based on iWave s SOM Product Part Number 4 16GB and 32GB eMMC are already valid...

Page 14: ...e i MX8 QM QP processors along with ARM core it supports dual 32 core GPU subsystems 4K H 265 capable VPU and dual failover ready display controllers 2 4K displays supporting multiple display output o...

Page 15: ...omised based on the requirement by contacting iWave support team 2 5 2 eMMC Flash The i MX8 QM QP SMARC SOM supports 16GB eMMC as default boot and storage device This is connected to eMMC0 version 5 1...

Page 16: ...is connected to QSPI0 controller of the i MX8 processor and operates at 1 8V Voltage levels The Xccela Flash U37 memory is physically located on Bottom side of the SMARC SOM The FlexSPI can be suppor...

Page 17: ...otive qualification according to ISO 16750 4 and is manufactured in line with ISO TS 16949 Connection to a host processor is through SDIO or High Speed UART interfaces The i MX8 SMARC SOM uses process...

Page 18: ...or J1 has standard pinout as per SMARC Specification V2 1 1 The interfaces which are available at 314pin SMARC Edge connector are explained in the following sections Figure 4 SMARC Edge Connector Numb...

Page 19: ...CSI0_DATA0_P GND P12 S12 MIPI_CSI0_DATA0_N MIPI_CSI1_DATA2_P P13 S13 GND MIPI_CSI1_DATA2_N P14 S14 MIPI_CSI0_DATA1_P GND P15 S15 MIPI_CSI0_DATA1_N MIPI_CSI1_DATA3_P P16 S16 GND MIPI_CSI1_DATA3_N P17 S...

Page 20: ...DMA_I2C1_SCL PCIE_SATA0_TX0_N P49 S49 DMA_I2C1_SDA GND P50 S50 AUD_SAI0_TXFS SPI2_CS1 PCIE_SATA0_RX0_P P51 S51 AUD_SAI0_TXD PCIE_SATA0_RX0_N P52 S52 AUD_SAI0_RXD GND P53 S53 AUD_SAI0_TXC SPI2_CS0 Note...

Page 21: ...Optionally SERDES1_TX GND P82 S83 GND PCIE_A_REFCLK_P P83 S84 PCIE_B_REFCLK_P PCIE_A_REFCLK_N P84 S85 PCIE_B_REFCLK_N GND P85 S86 GND PCIE0_A_RX0_P P86 S87 PCIE1_B_RX0_P PCIE0_A_RX0_N P87 S88 PCIE1_B_...

Page 22: ..._9 GPIO0_03 P117 S118 LVDS1 DSI1_CH1_TX2_N GPIO_10 GPIO0_04 P118 S119 GND GPIO_11 GPIO0_05 P119 S120 LVDS1 DSI1_CH1_TX3_P GND P120 S121 LVDS1 DSI1_CH1_TX3_N NC Note Optionally SM_PMIC_I2C_SCL P121 S12...

Page 23: ...T1 of i MX8 are connected to GBE0 and GBE1 ports of SMARC edge connector respectively The AR8031 integrates Atheros Green ETHOS power saving technologies and significantly saves power not only during...

Page 24: ...9 GBE0_MDI0 NA IO GBE Gigabit Ethernet MDI differential pair 0 negative P30 GBE0_MDI0 NA IO GBE Gigabit Ethernet MDI differential pair 0 positive For more details on GBE1 pinouts refer below Table SMA...

Page 25: ...Ethernet PHY and are optionally connected to SERDES0 and SERDES1 of SMARC edge connector respectively For more details on SERDES and MDIO pinouts refer below Table SMARC Pin No SMARC Edge Signal Name...

Page 26: ...OS SD Clock Note 1K pullup option is provided P37 GPIO_SDC1_PWR_EN GPIO1_19 MIPI_DSI0_GPI O0_01 BD28 O 3 3V CMOS SD Power enable P39 USDHC1_DATA0 USDHC1_DATA0 E37 IO 1 8 3 3V CMOS SD data 0 Note 10K p...

Page 27: ...to USB Hub P76 USB_HUB4_OC NA IO 3 3V CMOS 10K PU USB Port4 Over Current Indicator Note Connected to USB Hub S62 USB3_HUB2_TXP NA O USB SS USB3 0 Port3 Transmit Plus Note Connected to USB Hub S63 USB3...

Page 28: ...low table SMARC Pin No SMARC Edge Signal Name CPU Ball Name Pin Number Signal Type Termination Description P75 PCIE_A_RST_B GPIO4_29 PCIE_CTRL0_ PERST_B D20 O 3 3V CMOS PCIe Channel A Reset Out P77 PC...

Page 29: ...A 0 022uF AC Couple SATA Receive Lane Negative S54 SATA_ACT GPIO1_18 MIPI_DSI0_ GPIO0_00 BD30 O 3 3V CMOS GPIO used as SATA Activity indication 2 7 7 MIPI CSI Camera The i MX8 CPU supports two 4 lane...

Page 30: ...ector refer below table Exp Pin No Signal Name CPU Ball Name Pin Number Signal Type Termination Description 80 MIPI_CSI0_DATA2_P MIPI_CSI0_DAT A2_P BF24 I MIPI MIPI CSI0 differential data lane 2 posit...

Page 31: ...nd performed by means of software configuration i MX8 CPU supports HDMI 1 4 Specification HDMI 2 0a Specification DisplayPort Specification Version 1 3 and eDP Specification Version 1 4 protocols In i...

Page 32: ...0_DATA2 _EDP0_P BL9 O DP NC Note Optionally connected to Display Port Lane 0 Positive S94 DP0_N HDMI_TX0_DATA2 _EDP0_N BM8 O DP NC Note Optionally connected to Display Port Lane 0 Negative S95 DP0_AUX...

Page 33: ...he MIPI DSI controller provides an interface that allows communication with MIPI DSI compliant peripherals The MIPI DSI D PHY is a high frequency low power low cost source synchronous physical layer s...

Page 34: ...l data lane 2 negative Note Optionally connected to LVDS1_CH1 differential data lane 2 negative S120 MIPI_DSI1_TX3_P MIPI_DSI1_DATA3 _P BG27 or LVDS1_CH1_TX3 _P BM30 O MIPI MIPI DSI1 differential data...

Page 35: ...CLK _P BL27 or LVDS1_CH0_CLK _P BM36 O MIPI MIPI DSI0 differential Clock positive Note Optionally connected to LVDS1_CH0 differential Clock positive S135 MIPI_DSI0_CLK_N MIPI_DSI0_CLK _N BN27 or LVDS1...

Page 36: ...Master Clock for Audio codec S39 SAI1_TXFS SAI1_TXFS AV2 O 1 8V CMOS Serial Audio Interface Channel1 Frame Sync Left Right Clock S40 SAI1_TXD SAI1_TXD AU1 O 1 8V CMOS Serial Audio Interface Channel1...

Page 37: ...e Termination Description P54 SPI2_CS0 SPI2_CS0 AW1 or QSPI1A_SS0 J11 O 1 8V CMOS SPI2 Chip Select 0 Note Optionally connected to QSPI1A_ Chip Select 0 P55 QSPI1A_SS1 QSPI1A_SS1 G11 O 1 8V CMOS QSPI1A...

Page 38: ...1 8V CMOS UART0 Receiver P131 UART0_RTS_B UART0_RTS_B AU45 O 1 8V CMOS UART0 Request to Send P132 UART0_CTS_B UART0_CTS_B AW49 I 1 8V CMOS UART0 Clear to Send P134 UART3_TX UART3_TX AU47 O 1 8V CMOS U...

Page 39: ...Input output 6 P115 GPIO_7 GPIO0_01 SIM0_RST AP48 IO 1 8V CMOS SMARC General Purpose Input output 7 P116 GPIO_8 GPIO0_02 SIM0_IO AN45 IO 1 8V CMOS SMARC General Purpose Input output 8 P117 GPIO_9 GPI...

Page 40: ...used for General Purpose One LCD Display ID I2C can be used for General Purpose One Power Management I2C optional For more details of I2C pinouts on SMARC Edge connector refer below table SMARC Pin No...

Page 41: ...D NA I 5V CMOS 10K PU Power bad indication from Carrier board Module and Carrier power supplies shall not be enabled while this signal is held low by the Carrier S153 CARRIER_STBY NA O 1 8V CMOS 10K P...

Page 42: ...Description P147 P148 P149 P150 P151 P152 P153 P154 P155 P156 VDD_IN VDD_IN NA I 5V Power Supply Voltage P2 P9 P12 P15 P18 P32 P38 P47 P50 P53 P59 P68 P79 P82 P85 P88 P91 P94 P97 P100 P103 P120 P133 P...

Page 43: ...ilise extra interfaces which is not covered under SMARC specification V2 1 1 edge connector The SOM Expansion connector is placed on the bottom side of the SOM Figure 5 SMARC Expansion Connector Numbe...

Page 44: ...2_P 27 28 LVDS0_CH0_CLK_N GND 29 30 GND LVDS0_CH1_TX3_N 31 32 LVDS0_CH0_TX2_P LVDS0_CH1_TX3_P 33 34 LVDS0_CH0_TX2_N GND 35 36 GND LVDS0_CH1_TX2_N 37 38 LVDS0_CH0_TX3_P LVDS0_CH1_TX2_P 39 40 LVDS0_CH0_...

Page 45: ...ame CPU Ball Name Pin Number Signal Type Termination Description LVDS0 Channel0 26 LVDS0_CH0_CLK_P LVDS0_CH0_CLK _P BN41 O LVDS LVDS0 Channel0 Clock positive 28 LVDS0_CH0_CLK_N LVDS0_CH0_CLK _N BL41 O...

Page 46: ...n controller implementing the CAN protocol according to the CAN 2 0B protocol specification CAN0 and CAN1 of CPU are connected to SMARC edge connector and CAN2 is connected to expansion connector For...

Page 47: ...5 ESAI1_SCKR ESAI1_SCKR BD12 I 1 8V CMOS ESAI1 Clock Input 77 ESAI1_FSR ESAI1_FSR BE11 I 1 8V CMOS ESAI1 Frame Sync Input 81 ESAI1_TX0 ESAI1_TX0 BF10 O 1 8V CMOS ESAI1 Transmit 0 87 ESAI1_TX1 ESAI1_TX...

Page 48: ...ia Local Bus Device functionality is implemented with an MediaLB 3 pin interface single ended or MediaLB 6 pin interface differential however only one interface can be active at a time The MediaLB int...

Page 49: ...face HDMI RX interface is supported via board expansion connector The HDMI_RX Controller Supports up to 4K2K at 60Hz resolution and Compliant with HDCP2 2 and backward compatible with HDCP1 4 with up...

Page 50: ...fferential data lane 2 positive 56 VHDMI_RX_5V HDMI_RX0_MO N_5V BN11 Power VHDMI_RX_5V 67 HDMI_RX0_CEC HDMI_RX0_CEC BJ9 IO 3 3V CMOS HDMI Consumer Electronics Control 69 HDMI_RX_HPD HDMI_RX_HPD BF14 O...

Page 51: ...n Header J2 is physically located at the top of the board as shown below Figure 6 Fan Header Number of Pins 2 Connector Part 0530480210 from Molex Mating Connector 51021 0200 from Molex Compatible FAN...

Page 52: ...8V reference power is provided to pin 1 of the connectors to allow JTAG tool to automatically configure the logic signals for the right voltage The i MX8 CPU s SCU_UART0 and M4 Core1 UART or UART4 ca...

Page 53: ...JTAG test data input 6 GND Power Ground Note Optionally connected to SCU_UART0_RX 7 JTAG_TMS I 1 8V CMOS 10K PU JTAG test mode select 8 GND Power Ground Note Optionally connected to M41 UART0 TX and...

Page 54: ...on SMARC Edge Pin Number i MX8 CPU Pin Number Function 0 Function 1 Function 2 Function 3 GPIO Default State MIPI CSI0 S9 BE21 MIPI_CSI0 CKN MIPI_CSI0 CKN S8 BF20 MIPI_CSI0 CKP MIPI_CSI0 CKP S12 BE23...

Page 55: ...39 LVDS0 GPIO0 IO00 LVDS0 PWM0 OUT LSIO GPIO1 IO04 GPIO1_04 GPIO1_04 S127 BE37 LVDS0 I2C1 SCL DMA UART2 TX LSIO GPIO1 IO08 GPIO1_08 GPIO1_08 S133 BE35 LVDS0 I2C1 SDA DMA UART2 RX LSIO GPIO1 IO09 GPIO1...

Page 56: ...P LSIO GPIO5 IO18 GPIO5_18 CONN USDHC1 DATA3 P37 BD28 MIPI_DSI0 GPIO0 IO01 LSIO GPIO1 IO19 GPIO1_19 LSIO GPIO1 IO19 P33 BM24 MIPI_DSI1 GPIO0 IO00 MIPI_DSI1 PWM0 OUT LSIO GPIO1 IO22 GPIO1_22 LSIO GPIO1...

Page 57: ...PIO4_29 LSIO GPIO4 IO29 S76 G25 HSIO PCIE1 PERST_B LSIO GPIO5 IO00 GPIO5_00 LSIO GPIO5 IO00 SATA P48 B16 PCIE_SATA0_TX0_P PCIE_SATA0_TX0_P P49 C17 PCIE_SATA0_TX0_N PCIE_SATA0_TX0_N P51 A19 PCIE_SATA0_...

Page 58: ...OUT0 CAN P144 C5 DMA FLEXCAN0 RX LSIO GPIO3 IO29 GPIO3_29 DMA FLEXCAN0 RX P143 H6 DMA FLEXCAN0 TX LSIO GPIO3 IO30 GPIO3_30 DMA FLEXCAN0 TX P146 E5 DMA FLEXCAN1 RX LSIO GPIO3 IO31 GPIO3_31 DMA FLEXCAN1...

Page 59: ...ies Pvt Ltd Interface Function SMARC Edge Pin Number i MX8 CPU Pin Number Function 0 Function 1 Function 2 Function 3 GPIO Default State Control Signal S145 BC53 SCU GPIO0 IOXX_PMIC_MEM C_ON SCU GPIO0...

Page 60: ...S0_CH0_TX0_P 52 BL43 LVDS0_CH0_TX1_N LVDS0_CH0_TX1_N 50 BN43 LVDS0_CH0_TX1_P LVDS0_CH0_TX1_P 34 BK44 LVDS0_CH0_TX2_N LVDS0_CH0_TX2_N 32 BM44 LVDS0_CH0_TX2_P LVDS0_CH0_TX2_P 40 BL45 LVDS0_CH0_TX3_N LVD...

Page 61: ...ESAI1 FSR 65 BF12 AUD ESAI1 FST LSIO GPIO2 IO05 AUD ESAI1 FST 75 BD12 AUD ESAI1 SCKR LSIO GPIO2 IO06 AUD ESAI1 SCKR 92 AY10 AUD ESAI1 SCKT AUD SAI2 RXC LSIO GPIO2 IO07 AUD ESAI1 SCKT 81 BF10 AUD ESAI...

Page 62: ...3 MLB 68 D32 CONN MLB PADP_CLK CONN MLB PADP_CLK 70 E33 CONN MLB PADN_CLK CONN MLB PADN_CLK 74 D30 CONN MLB PADP_S CONN MLB PADP_S 76 E31 CONN MLB PADN_S CONN MLB PADN_S 62 F34 CONN MLB PADP_D CONN ML...

Page 63: ...definite exposure to an applied VDD_IN that may vary over the 4 5V to 5 25V range without damage and it will operate over the entire VDD_IN range of 4 5V to 5 25V Ten pins are allocated to VDD_IN The...

Page 64: ...hernet Eth0 and Eth1 VDD_IN 1 66A 8 3W eMMC to Standard SD file transfer VDD_IN 1 8A 9W eMMC to USB3 0 file transfer VDD_IN 2 01A 10 05W eMMC to SATA file transfer VDD_IN 1 96A 9 8W Bluetooth file tra...

Page 65: ...eat Sink Heat Spreader For any highly integrated System On Modules thermal design is a very important factor As IC s size is decreasing and performance of module is increasing by rising processor freq...

Page 66: ...REL1 0 Page 66 of 71 i MX8 SMARC SOM Hardware User Guide iWave Systems Technologies Pvt Ltd Figure 9 Mechanical dimension of Heat Sink Figure 10 Mechanical dimension of Heat Spreader...

Page 67: ...components and manufactured on lead free production process 3 2 4 Electrostatic Discharge iWave s i MX8 SMARC SOM is sensitive to electro static discharge and so high voltages caused by static electr...

Page 68: ...SOM PCB thickness is 1 2mm 0 15mm top side maximum height component is 3 5mm debug Connector which is optional in default configuration hence 3 4mm FAN header will be the maximum height on Top side i...

Page 69: ...ith boot code Without Wi Fi BT 40 C to 85 C iW Rainbow G27M i MX8 SMARC SOM Industrial grade with Expansion Connector iW G27M SCQM 4L004G E016G LIG i MX8 Quad Max 4GB LPDDR4 16GB eMMC flash with Linux...

Page 70: ...i MX8 CPU based SMARC SOM and its features Being a Nano ITX form factor with 120mm x 120mm size the carrier board is highly packed with all necessary interfaces on board connectors to validate complet...

Page 71: ...REL1 0 Page 71 of 71 i MX8 SMARC SOM Hardware User Guide iWave Systems Technologies Pvt Ltd...

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