REL1.0
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i.MX8 SMARC SOM Hardware User Guide
iWave Systems Technologies Pvt. Ltd.
The i.MX8 CPU Supports three CAN interface and CAN0 and CAN1 are connected to SMARC Edge connector and CAN3
is connected to Board Expansion connector.
For more details of CAN pinouts on SMARC Edge connector, refer below table:
SMARC
Pin No.
SMARC Edge
Signal Name
CPU Ball Name/
Pin Number
Signal Type/
Termination
Description
P143
FLEXCAN0_TX
FLEXCAN0_TX/
H6
O, 1.8V CMOS
CAN 0 Transmitter.
P144
FLEXCAN0_RX
FLEXCAN0_RX/
C5
I, 1.8V CMOS
CAN 0 Receiver.
P145
FLEXCAN1_TX
FLEXCAN1_TX/
G7
O, 1.8V CMOS
CAN 1 Transmitter.
P146
FLEXCAN1_RX
FLEXCAN1_RX/
E5
I, 1.8V CMOS
CAN 1 Receiver.
2.7.15
I2C Interface
SMARC Specification V2.1.1 supports Five I2C but i.MX 8QM SOM supports only four I2C in default configuration and
fifth I2C as optional which are listed down:
•
One General Purpose I2C
•
Two Camera I2C (can be used for General Purpose)
•
One LCD Display ID I2C (can be used for General Purpose)
•
One Power Management I2C (optional)
For more details of I2C pinouts on SMARC Edge connector, refer below table:
SMARC
Pin No.
SMARC Edge
Signal Name
CPU Ball Name/
Pin Number
Signal Type/
Termination
Description
S48
I2C_GP_CK
DMA_I2C1_SCL/
AY52
O, 1.8V CMOS
2.2K PU
General Purpose I2C Clock.
S49
I2C_GP_DAT
DMA_I2C1_SDA/
AV52
IO, 1.8V CMOS
2.2K PU
General Purpose I2C Data.
S1
I2C_CAM1_CK
MIPI_CSI1_I2C0_SCL/
BN17
O, 1.8V CMOS
2.2K PU
Secondary Camera Purpose I2C
Clock.
S2
I2C_CAM1_DAT
MIPI_CSI1_I2C0_SDA/
BE15
IO, 1.8V CMOS
2.2K PU
Secondary Camera Purpose I2C
Data.
S5
I2C_CAM0_CK
MIPI_CSI0_I2C0_SCL/
BH24
O, 1.8V CMOS
2.2K PU
Primary Camera Purpose I2C
Clock.
S7
I2C_CAM0_DAT
MIPI_CSI0_I2C0_SDA/
BN19
IO, 1.8V CMOS
2.2K PU
Primary Camera Purpose I2C
Clock.
S139
I2C_LCD_CK
LVDS_I2C_SCL/
BD38
O, 1.8V CMOS
2.2K PU
Display Purpose I2C Clock.
S140
I2C_LCD_DAT
LVDS_I2C_SDA/
BD36
IO, 1.8V CMOS
2.2K PU
Display Purpose I2C Clock.
P121
NC
(I2C_PM_CK)
PMIC_I2C_SCL/
AY46
O, 1.8V CMOS
2.2K PU
NC.
Note: Optionally connected to
PMIC_I2C_SCL
