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iWave Systems Technologies Pvt. Ltd.

i.MX6UL/i.MX6ULL SODIMM SOM Hardware User Guide

2.8

i.MX6UL/i.MX6ULL Pin Multiplexing on SODIMM Edge

The i.MX6UL/i.MX6ULL

CPU’s IO pins ha

ve many alternate functions and can be configured to any one of the alternate functions based on the requirement.

Also most of the i.MX6UL/i.MX6ULL

CPU’s IO pins can be configured as GPIO if required.

The below table provides the details of i.MX6UL/i.MX6ULL CPU pin

connections to the SOM edge connector with selected pin function and available alternate functions. This table has been prepared by referring NXP

’s i.MX6UL

Applications Processor Reference Manual (Rev0).

Important Note: It is strongly recommended to use the pin function same as selected in the i.MX6UL/i.MX6ULL SOIDMM SOM Edge connector

for iWave’s BSP

reusability and to have compatible SODIMM modules in future for upgradability.

Table 7: IOMUX Configuration of i.MX6UL/i.MX6ULL SODIMM SOM Edge Connector interfaces

Interface/

Function

SODIMM

Edge Pin No

i.MX6UL/

i.MX6ULL CPU

Pad Name

ALT0

ALT1

ALT2

ALT3

ALT4

ALT5

ALT6

ALT7

ALT8

Default/Reset

State

Debug

UART

(UART1)

117

UART1_RX_D
ATA

UART1_RX

ENET1_RDA
TA03

I2C3_SDA

CSI_DATA03

GPT1_CLK

GPIO1_IO17

SPDIF_IN

UART1_RX

118

UART1_TX_D
ATA

UART1_TX

ENET1_RDA
TA02

I2C3_SCL

CSI_DATA02

GPT1_COMP
ARE1

GPIO1_IO16

SPDIF_OUT

UART1_TX

Data

UART5

102

UART5_RX_D
ATA

UART5_RX

ENET2_COL

I2C2_SDA

CSI_DATA15

CSU_CSU_IN
T_DEB

GPIO1_IO31

ECSPI2_MIS
O

UART5_RX

103

UART5_TX_D
ATA

UART5_TX

ENET2_CRS

I2C2_SCL

CSI_DATA14

CSU_CSU_AL
ARM_AUT00

GPIO1_IO30

ECSPI2_MOS
I

UART5_TX

GPIO1_IO09

PWM2_OUT

WDOG1_W
DOG_ANY

SPDIF_IN

CSI_HSYNC

USDHC2_RE
SET_B

GPIO1_IO09

USDHC1_RE
SET_B

UART5_CTS_
B

GPIO1_IO09

GPIO1_IO08

PWM1_OUT

WDOG1_W
DOG_B

SPDIF_OUT

CSI_VSYNC

USDHC2_VS
ELECT

GPIO1_IO08

CCM_PMIC_
RDY

UART5_RTS_
B

GPIO1_IO08

Data

UART2

UART2_RX_D
ATA

UART2_RX

ENET1_TDA
TA03

I2C4_SDA

CSI_DATA07

GPT1_CAPT
URE2

GPIO1_IO21

SJC_DONE

ECSPI3_SCLK

UART2_RX

UART2_TX_D
ATA

UART2_TX

ENET1_TDA
TA02

I2C4_SCL

CSI_DATA06

GPT1_CAPT
URE1

GPIO1_IO20

ECSPI3_SS0

UART2_TX

Summary of Contents for iW-RainboW-G18M

Page 1: ...REL1 2 Page 1 of 55 i MX6UL i MX6ULL SODIMM SOM Hardware User Guide iWave Systems Technologies Pvt Ltd iW RainboW G18M i MX6UL i MX6ULL SODIMM SOM Hardware User Guide...

Page 2: ...133 134 136 details are updated in Table 5 CPU Pad Name and ALT0 pin details are updated in Table 7 for pins 62 63 66 70 93 104 110 120 Orderable Product Part Numbers are updated in Table 12 Non subst...

Page 3: ...on errata and associated issues Trademarks All registered trademarks product names mentioned in this publication are the property of their respective owners and used for identification purposes only C...

Page 4: ...IMM PCB Edge Connector 17 2 6 1 UART Interface 18 2 6 2 CAN Interface 18 2 6 3 SD Interface 18 2 6 4 Parallel RGB Display Interface 18 2 6 5 Parallel Camera Interface 19 2 6 6 I2S Audio Interface 19 2...

Page 5: ...on 47 3 2 Environmental Characteristics 48 3 2 1 Environmental Specification 48 3 2 2 RoHS Compliance 48 3 2 3 Electrostatic Discharge 48 3 3 Mechanical Characteristics 49 3 3 1 SODIMM SOM Mechanical...

Page 6: ...e 9 Mechanical dimension of SODIMM SOM Side View 50 Figure 10 SODIMM SOM Insertion procedure 53 Figure 11 SODIMM SOM Removal procedure 53 Figure 12 i MX6UL i MX6ULL SODIMM SOM Development Platform 54...

Page 7: ...ution on i MX6UL i MX6ULL platform SODIMM module has a form factor of 67 6mm x 29mm and provides the functional requirements for an embedded application A single ruggedized SODIMM connector provides t...

Page 8: ...grated Circuit PTH Plated Through hole PWM Pulse Width Modulation PXP Pixel Pipeline QSPI Quad Serial Peripheral Interface RMII Reduced Media Independent Interface ROM Read Only Memory RTC Real Time C...

Page 9: ...Metal Oxide Semiconductor Signal DIFF Differential Signal TMDS Transition Minimized Differential Signalling OD Open Drain Signal OC Open Collector Signal Analog Analog Signal Power Power Pin PU Pull...

Page 10: ...are using and CPU Pad name is SD1_DATA1 If CPU pin functionality name and pad name is different Signal name is mentioned as Functionality name CPU Pad name Example CAN1_RXD UART3_RTS_B In this signal...

Page 11: ...eCSPI x 1 ENET2 uSD Connector1 Optional eMMC1 Optional USB OTG1 USB OTG2 USB OTG2 HS PHY USB OTG1 HS PHY RMII 10 100Mbps Ethernet PHY I2S3 SAI2 JTAG uSDHC1 SD 4bit UART1 Debug UART UART2 UART3 Data UA...

Page 12: ...Flash Expandable 4GB eMMC Flash Optional 1 Micro SD slot Optional 2 QSPI Flash Optional 3 Network Communication 10 100Mbps Ethernet PHY x 2 Ports SODIMM PCB Edge Interfaces Debug UART Data UART x 3 P...

Page 13: ...d in the SOM NAND flash and eMMC on SOM cannot be used 3 Since NAND Flash and QSPI are multiplexed in same pins on i MX6UL i MX6ULL CPU if NAND Flash feature is required in the SOM QSPI on SOM cannot...

Page 14: ...ent processor family featuring an advanced implementation of a single ARM Cortex A7 core The Block Diagram of i MX6UL CPU from the NXP s i MX6UL datasheet is shown below for reference Figure 2 i MX6UL...

Page 15: ...ies Pvt Ltd i MX6UL CPU has many sub version CPUs i MX6UL0 i MX6UL1 i MX6UL2 i MX6UL3 Also i MX6ULL CPU has many sub version CPUs i MX6ULL0 i MX6ULL1 i MX6ULL2 The difference between these CPUs from N...

Page 16: ...o three buck converters six linear regulators RTC supply and coin cell charger i MX6UL i MX6ULL CPU s I2C1 interface is used for PMIC programming I2C address for PMIC is 0x08 2 5 Memory 2 5 1 DDR3L SD...

Page 17: ...available at SODIMM Edge connector are explained in the following sections Figure 4 SODIMM PCB Edge Connector Number of Pins 200 Connector Part Not Applicable On Board PCB Edge connector Mating Conne...

Page 18: ...FLEXCAN1 and FLEXCAN2 module is used for CAN interface which supports CAN protocol according to the CAN 2 0B protocol specification It supports programmable bit rate up to 1 Mb sec with both standard...

Page 19: ...ly from an audio master clock or supplied externally Also the SAI transmitter and receiver can be configured to operate with synchronous bit clock and frame sync For more details refer SODIMM Edge con...

Page 20: ...LED control signals to SODIMM Edge i MX6UL i MX6ULL SODIMM SOM supports two KSZ8081RNBI Ethernet PHY from Micrel These PHY s are interfaced with CPU using ENET1 and ENET2 interface correspondingly an...

Page 21: ...s 138 147 on Table 5 2 6 12 Tamper Interface i MX6UL3 SODIMM SOM supports upto seven external Tamper detection signals on SODIMM Edge connector External Tamper Detection is a special mechanism provide...

Page 22: ...mode signals on SODIMM Edge Connector BOOT_MODE is initialized by sampling the BOOT_MODE0 and BOOT_MODE1 inputs on the rising edge of POR_B These Boot mode selection signals are connected to SODIMM Ed...

Page 23: ...in can be used to reset the i MX6UL i MX6ULL CPU by connecting push button in the carrier board For more details refer SODIMM Edge connector pin 187 on Table 5 2 6 18 Power Control Signal i MX6UL i MX...

Page 24: ...ve differential pair 1 positive 9 UART3_TX_DATA UART3_TX_DATA H17 O 3 3V CMOS UART3 serial data transmitter 10 NC NA NC 11 ETH1_LINK_LED0 NA Ethernet link status LED 12 ETH1_SPEED_LED1 NA Ethernet spe...

Page 25: ...M from Ethernet PHY is connected to this pin through resistor and default populated Note ENET2_TX_CLK from CPU is optionally connected to this pin through resistor and default not populated 36 ETH2_TX...

Page 26: ...NA Default NC Note ENET2_RX_EN from CPU is optionally connected to this pin through resistor and default not populated 46 VIN_3V3 NA I 3 3V Power Supply Voltage 47 GPIO5_IO0 SNVS_TA MPER0 SNVS_TAMPER...

Page 27: ...R9 IO 3 3V CMOS Tamper Detection Pin 1 Or General purpose input output Important Note In i MX6UL3 SODIMM SOM this pin can be used as only Tamper functionality In all other i MX6UL i MX6ULL CPU version...

Page 28: ...t connected to On SOM Ethernet PHY s 81 USB_OTG_DP USB_OTG_DP U15 IO DIFF USB OTG1 data positive 82 NC NA NC 83 USB_OTG_DN USB_OTG_DN T15 IO DIFF USB OTG1 data negative 84 NC NA NC 85 NC NA NC 86 GPIO...

Page 29: ...ART3 Ready to receive data function through resistor and default not populated 98 UART2_TX_DATA UART2_TX_DATA J17 O 3 3V CMOS UART2 serial data transmitter 99 UART2_RX_DATA UART2_RX_DATA J16 I 3 3V CM...

Page 30: ...te Same signal is optionally connected to 19th pin of SODIMM Edge connector 116 I2C1_SCL UART4_TX_ DATA _SODIMM UART4_TX_DATA G17 O 3 3V OD 4 7K PU I2C1 clock Note Same signal is optionally connected...

Page 31: ...In i MX6UL3 SODIMM SOM this pin can be used as only Tamper functionality In all other i MX6UL i MX6ULL CPU version SODIMM SOM this pin can be used as only GPIO functionality 135 CCM_CLK1_P CCM_CLK1_P...

Page 32: ...Parallel LCD data 16 Red data0 149 LCD_DATA171 LCD_DATA17 B13 O 3 3V CMOS 10K PD Parallel LCD data 17 Red data1 150 LCD_DATA181 LCD_DATA18 A13 O 3 3V CMOS 10K PD Parallel LCD data 18 Red data2 151 GND...

Page 33: ...31 LCD_DATA03 D10 O 3 3V CMOS 10K PD Parallel LCD data 3 Blue data3 171 LCD_DATA041 LCD_DATA04 C10 O 3 3V CMOS 1K PU Parallel LCD data 4 Blue data4 172 LCD_DATA051 LCD_DATA05 B10 O 3 3V CMOS 10K PD Pa...

Page 34: ...don t add any external pullup in carrier board on this pin Make sure to use this pin in carrier board to select desired boot mode by driving only low if required 185 GND NA Power Ground 186 GND NA Pow...

Page 35: ...NA Power Ground 199 JTAG_TMS SAI2_MCLK JTAG_TMS P14 I 3 3V CMOS JTAG Test Mode Select Note Same signal is also connected to 64th pin of SODIMM edge connector 200 USB_OTG1_VBUS USB_OTG1_VBUS T12 I Powe...

Page 36: ...d in the SOM NAND flash and Micro SD on SOM cannot be used 2 7 2 Micro SD Slot i MX6UL i MX6ULL SODIMM SOM supports Micro SD slot to connect Micro SD card for Mass storage and also can be used as Boot...

Page 37: ...d configuration This is the optional feature and will not be populated in default configuration PMIC OTP Header is physically located on topside of the SOM as shown below Figure 5 PMIC OTP Header Numb...

Page 38: ...L i MX6ULL SODIMM SOM Edge Connector interfaces Interface Function SODIMM Edge Pin No i MX6UL i MX6ULL CPU Pad Name ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 ALT8 Default Reset State Debug UART UART1 11...

Page 39: ...T1_COMP ARE2 ECSPI3_MOS I ECSPI3_MOS I UART2_CTS_B 175 UART2_RTS_B ENET1_COL FLEXCAN2_ RX CSI_DATA0 9 GPT1_COMP ARE3 GPIO1_IO23 SJC_FAIL ECSPI3_MIS O ECSPI3_MIS O UART2_RTS_B SD1 109 SD1_CLK USDHC1_CL...

Page 40: ...SRC_BT_CFG 04 SAI1_TX_DA TA LCDIF_DATA04 172 LCDIF_DATA0 5 LCDIF_DATA 05 UART8_RTS _B ENET2_1588 _EVENT2_O UT SPDIF_OUT GPIO3_IO10 SRC_BT_CFG 05 ECSPI1_SS1 LCDIF_DATA05 173 LCDIF_DATA0 6 LCDIF_DATA 06...

Page 41: ...USDHC2_CM D LCDIF_DATA18 152 LCDIF_DATA1 9 LCDIF_DATA 19 PWM6_OUT WDOG1_W DOG_ANY CSI_DATA11 EIM_DATA1 1 GPIO3_IO24 SRC_BT_CFG 27 USDHC2_CL K LCDIF_DATA19 153 LCDIF_DATA2 0 LCDIF_DATA 20 UART8_TX ECSP...

Page 42: ...SDHC2_DA TA6 SIM2_PORT 1_SVEN ECSPI1_MOS I EIM_AD06 GPIO4_IO27 SAI1_RX_DA TA USDHC1_RE SET_B CSI_DATA08 120 CSI_DATA07 CSI_DATA07 USDHC2_DA TA7 SIM2_PORT 1_TRXD ECSPI1_MIS O EIM_AD07 GPIO4_IO28 SAI1_T...

Page 43: ...PT1_COM PARE3 USB_OTG2 _OC USDHC1_CD _B GPIO1_IO03 CCM_DI0_EX T_CLK SRC_TESTER _ACK UART1_RX GPIO1_IO03 ENET2 RMII Interface Optional 42 ENET2_RX_DA TA0 ENET2_RDA TA00 UART6_TX SIM1_PORT 0_TRXD I2C3_S...

Page 44: ...d Reserved Reserved GPIO5_IO00 Reserved Reserved Reserved SNVS_TAMPER 0 68 SNVS_TAMPE R1 snvs_lp_wra pper1 Reserved Reserved Reserved Reserved GPIO5_IO01 Reserved Reserved Reserved SNVS_TAMPER 1 73 SN...

Page 45: ...Power Input Requirement The below table provides the Power Input Requirement of i MX6UL i MX6ULL SODIMM SOM Table 8 Power Input Requirement Sl No Power Rail Min V Typical V Max V Max Input Ripple 1 V...

Page 46: ...the same time or before VRTC_3V0 goes down Figure 6 i MX6UL i MX6ULL SODIMM SOM Power Sequence Table 9 Power Sequence Timing Item Description Value T1 VRTC_3V0 rise time to VIN_3V3 rise time 0 ms T2...

Page 47: ...cro SD file transfer Dhrystone benchmark application 100Mbps Ethernet ping on ENET1 ENET2 VIN_3V3 0 265 0 875W Low Power Mode Power Consumption System Idle Mode VIN_3V3 0 031 0 102W Deep Sleep Mode VI...

Page 48: ...s system enclosure air circulation in the system system power supply etc Based on the system design specific heat dissipating approach might be required from system to system It is recommended to do t...

Page 49: ...Mechanical Dimensions i MX6UL i MX6ULL SODIMM SOM PCB size is 67 6mm x 29mm x 1mm SODIMM SOM mechanical dimension is shown below Please refer the JEDEC Physical standard DDR S O DIMM specification fo...

Page 50: ...ickness is 1 0 1mm top side maximum height component is Capacitor C22 1 45mm followed by CPU 1 32mm and bottom side maximum height component is Capacitor C68 1 45mm followed by Diode D3 1 0mm Please r...

Page 51: ...256MB NAND Flash with Linux Commercial iW G18M SM1S 3D256M N256M BC With i MX6UL3 Commercial grade CPU 256MB RAM 256MB NAND Flash with Boot Code Commercial i MX6UL2 CPU based SODIMM SOMs iW G18M SM1G...

Page 52: ...dustrial grade CPU 256MB RAM 256MB NAND Flash with Boot Code Industrial iW G18M SMY1 3D256M N256M LCA With i MX6ULL1 Commercial grade CPU 256MB RAM 256MB NAND Flash with Linux Commercial iW G18M SMY1...

Page 53: ...ntil you feel it slip down into the socket With the SODIMM SOM properly seated in the socket rotate the SOM downward as indicated in the illustration Continue pressing downward until the clips at each...

Page 54: ...board for complete validation of i MX6UL i MX6ULL SODIMM SOM functionality with complete BSP support Being a Pico ITX form factor with 100mmx72mm size the i MX6UL i MX6ULL SODIMM Development Platform...

Page 55: ...REL1 2 Page 55 of 55 iWave Systems Technologies Pvt Ltd i MX6UL i MX6ULL SODIMM SOM Hardware User Guide...

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