REL1.2
Page 31 of 55
i.MX6UL/i.MX6ULL SODIMM SOM Hardware User Guide
iWave Systems Technologies Pvt. Ltd.
Pin
No.
SODIMM Edge
Connector Pin Name
i.MX6UL/i.MX6ULL
Ball Name/
Pin Number
Signal Type/
Termination
Description
129
NC
NA
-
NC.
130
NC
NA
-
NC.
131
GND
NA
Power
Ground.
132
GPIO3_IO04(LCD_RES
ET)
LCD_RESET/
E9
IO, 3.3V CMOS General purpose input/output.
133
GPIO5_IO7(SNVS_TA
MPER7)
SNVS_TAMPER7/
N10
IO, 3.3V CMOS Tamper Detection Pin 7 (Or) General purpose
input/output.
Important Note: In i.MX6UL3 SODIMM SOM,
this pin can be used as only Tamper
functionality. In all other i.MX6UL/i.MX6ULL
CPU version SODIMM SOM, this pin can be
used as only GPIO functionality.
134
GPIO5_IO8(SNVS_TA
MPER8)
SNVS_TAMPER8/
N9
IO, 3.3V CMOS Tamper Detection Pin 8 (Or) General purpose
input/output.
Important Note: In i.MX6UL3 SODIMM SOM,
this pin can be used as only Tamper
functionality. In all other i.MX6UL/i.MX6ULL
CPU version SODIMM SOM, this pin can be
used as only GPIO functionality.
135
CCM_CLK1_P
CCM_CLK1_P/
P17
IO, DIFF
Clock Controller Module positive Clock.
136
GPIO5_IO9(SNVS_TA
MPER9)
SNVS_TAMPER9/
R6
IO, 3.3V CMOS Tamper Detection Pin 9 (Or) General purpose
input/output.
Important Note: In i.MX6UL3 SODIMM SOM,
this pin can be used as only Tamper
functionality. In all other i.MX6UL/i.MX6ULL
CPU version SODIMM SOM, this pin can be
used as only GPIO functionality.
137
CCM_CLK1_N
CCM_CLK1_N/
P16
IO, DIFF
Clock Controller Module negative Clock.
138
NAND_DQS/QSPI_A_S
S0_B/PWM5_OUT
NAND_DQS/
E6
O, 3.3V CMOS
Pulse Width Modulation 5 Output.
139
NC
NA
-
Default NC.
Note: GPIO1_IO05 is optionally connected to
this pin (for OTG2_ID) through resistor and
default not populated.
140
USB_OTG2_PWR(GPIO
1_IO02)
GPIO1_IO02/
L14
O, 3.3V CMOS
Power enable signal to control USB Power
switch, to supply VBUS voltage
