REL1.2
Page 11 of 55
i.MX6UL/i.MX6ULL SODIMM SOM Hardware User Guide
iWave Systems Technologies Pvt. Ltd.
2.
ARCHITECTURE AND DESIGN
This section provides detailed information about the i.MX6UL/i.MX6ULL SODIMM SOM Features and Hardware
architecture with high level block diagram. Also this section provides detailed information about SODIMM edge
connector pin assignment and usage.
2.1
i.MX6UL/i.MX6ULL SODIMM SOM Block Diagram
DDR3 RAM
(256MB)
NAND Flash
1
(256MB)
SODIMM
PCB Edge
Connector
(200Pin)
10/100Mbps
Ethernet1
RMII
I2C x 1
PWM x 2
ENET1
I2C1
PWM4 &
PWM5
Tamper/
GPIOs
NAND (8bit)
DDR3 (16bit)
10/100Mbps
Ethernet PHY
MMDC
RAWNAND/
uSDHC2/
QSPI_A
LCDIF
iW-RainboW-G18M-i.MX6UL/i.MX6ULL SODIMM SOM Block Diagram
Tamper/GPIOs
4
Power to
Peripherals
3.3V
CSI0
On-Board
PMIC
RGB LCD (24bpp)
Camera (8bit)/eCSPI x 1
ENET2
uSD
Connector
1
(Optional)
eMMC
1
(Optional)
USB OTG1
USB OTG2
USB OTG2
HS PHY
USB OTG1
HS PHY
RMII
10/100Mbps
Ethernet PHY
I2S
3
SAI2/
JTAG
uSDHC1
SD (4bit)
UART1
Debug UART
UART2 &
UART3
Data UART (with CTS & RTS)
FLEXCAN1,
FLEXCAN2
CAN x 2
QSPI
1
(Optional)
1
For On-SOM storage, any one of the below
options can be selected.
•
8bit NAND Flash (Default)
•
8bit eMMC and QSPI flash
•
4bit uSD and QSPI Flash
10/100Mbps
Ethernet2
RMII/Data UART x 3/Keypad (4x4)
2
MMC (8bit)
SD (4bit)
QSPI (4bit)
JTAG
3
UART5
Data UART x 2
BootMode0 &
BootMode1
Boot Mode
CPU
i.MX6UL/
i.MX6ULL
CCM_CLK
General purpose Clock
2
If 2nd Ethernet support is not required on the
SODIMM Edge Connector, RMII interface or
Data UART x 3ports or 4x4 Keypad interface
can be used in the SODIMM Edge.
3
Since Audio and JTAG interface signals are
multiplexed in same pins on CPU, either one
interface only can be used at a time.
4
Tamper functionality is supported only in
i.MX6UL3 version CPU.
Figure 1: i.MX6UL/i.MX6ULL SODIMM SOM Block Diagram
