Intersil ISL98001, Installation And Operation Manual

Page: 19 / 29

5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
EDID EEPROM 1
EDID EEPROM 2
LA_POD_3
LA_POD_0 LA_POD_2
LA_POD_1
LOGIC ANALYZER HEADERS
Note: Place EDID EEPROM on
bottom layer
ISL98001 1.0
ISL98001 Evaluation Board
B
3 7 Tuesday, March 29, 2005
Title
Size Document Number Rev
Date: Sheet of
DDC_SDA1
DDC_SCL1
DDC_SCL2
DDC_SDA2
GS_D1
RP_D4
RP_D2
GP_D7
BS_D3
BS_D2
RP_D5
RP_D6
GP_D2
GS_D6
BS_D7
BS_D1
BP_D2
GP_D3
BS_D6
DATACLK_S
BP_D[7..0]
GS_D[7..0]
GS_D2
GP_D6
GP_D[7..0]
BP_D5
RP_D1
GP_D5
GS_D4
BP_D1
GS_D3
RP_D3
BP_D6
BS_D4
BS_D0
GP_D4
BP_D4
GP_D1
BP_D3
GS_D0
BP_D0
GS_D5
RP_D0
BP_D7 RP_D7
BS_D5
GS_D7
GP_D0
BS_D[7..0]
RP_D[7..0]
RS_D5
RS_D[7..0]
RS_D6
RS_D1
RS_D4
RS_D7
RS_D0
RS_D2
RS_D3
RP_D[7..0] (1,5)
GP_D[7..0] (1,5)
GS_D[7..0] (1,5)
BP_D[7..0] (1,5)
BS_D[7..0] (1,5)
DATACLK_S (1,5)
DATACLKB_S (1,5)
HSOUT_S (1,5)
VSOUT_S (1,5)
HSYNCOUT_S (1,5)
VSYNCOUT_S (1,5)
DDC_SDA2 (2)
DDC_SCL2 (2)
DDC_SDA1 (1)
DDC_SCL1 (1)
RS_D[7..0] (1,5)
DATACLK_S (1,5)
5V_VGA1
5V_VGA2
U4
SMT
1
2
3
4
5
6
7
8
A0
A1
A2
Gnd SDA
SCL
WP
VCC
U3
SMT
1
2
3
4
5
6
7
8
A0
A1
A2
Gnd SDA
SCL
WP
VCC
R26
4.7K
HDR23
HEADER 8x2/SM
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
HDR18
HEADER 8x2/SM
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
C28
0.1uF
JP13
1
2
HDR16
HEADER 8x2/SM
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
R25
4.7K
HDR22
HEADER 8x2/SM
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
HDR15
HEADER 8x2/SM
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
HDR17
HEADER 8x2/SM
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
C22
0.1uF
HDR21
HEADER 8x2/SM
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
R23
4.7K R22
4.7K