background image

5

5

4

4

3

3

2

2

1

1

D

D

C

C

B

B

A

A

Cypress USB Address Bus

Cypress USB Data Bus

DVI 24bits DataBus

DVI DE, Clock and Sync.

ISL98001LC

1.0

ISL98001 Evaluation Board

B

5

7

Tuesday, March 29, 2005

Title

Size

Document Number

Rev

Date:

Sheet

of

HSYNCOUT_S

VSOUT_S

VSYNCOUT_S

CY_CLKOUT

RP_D[7..0]

BS_

D

3

RP

_D5

BS_

D

6

RP

_D2

RP

_D0

RP

_D3

DATACLK_S

RP

_D6

XTALCLKOUT

RP

_D1

RP

_D7

BS_D[7..0]

BS_

D

2

BS_

D

7

BS_

D

4

DATACLKB_S

RP

_D4

BS_

D

5

BS_

D

1

BS_

D

0

HSOUT_S

DA

T

A

7

DA

T

A

6

DA

T

A

4

DA

T

A

3

DA

T

A

2

DA

T

A

1

DA

T

A

5

DA

T

A

0

DATA[0..7]

TDO

TMS
TCK

TDI

TD

I

TMS

TC

K

TD

O

DVOB_CLK0

ADDR8

ADDR6

DVOB_BLANK

ADDR11

ADDR0

ADDR9

ADDR7

DVOB_D[0..23]

ADDR12

ADDR10

ADDR1

ADDR13

ADDR2

ADDR14

ADDR3

ADDR15

ADDR4

DVOB_CLK1

DVOB_VSYNC

ADDR[0..15]

DVOB_HSYNC

ADDR5

M1
M2

M0

M0

M1

M2

CY

_DONE

CY

_CLK

CY

_P

ROG

CY

_I

NI

T

B

CY_PROG
CY_CLK
CY_DIN0

CY_INITB
CY_DONE

TCK
TDO

TDI

TMS

DV

OB

_B

LA

NK

CY

_DI

N

1

CY

_DI

N

0

CY_DIN1

CY

_B

US

Y

CY_BUSY

SP1
SP2

SP3
SP4
SP5
SP6
SP7

SP8

SP9

SP1

0

SP1

1

SP1

2

SP1

3

SP15
SP14

RD#

WR#

SP18

SP19

SP20

SP2

1

SP2

2

SP2

3

SP2

4

SP2

5

SP2

6

SP2

7

SP2

8

GS_D[7..0]

RS_D[7..0]

GS_D1

RS_D5

GS_D7

GS_D2

RS_D3

GS_D0

GP_D6

GS_D4

GS_D3

RS_D1

RS_D7

RS_D2

GP_D0

GP_D2

RS_D6

GP_D5

GP_D3

GP_D[7..0]

GS_D6

RS_D0

GP_D4

RS_D4

GS_D5

GP_D7

GP_D1

BP_D4

BP_D6

BP_D2

BP_D7

BP_D[7..0]

BP_D1

BP_D0

BP_D3

BP_D5

RST_DVI

SP1

SP21

SP24

SP28

SP2

SP26

SP25

SP23

SP17

SP13

SP12

SP5

SP27

SP11

SP8

SP19

SP6

SP15

SP7

SP10

3.3V

SP14

SP4

SP3

3.3V

SP9

SP16
SP18
SP20
SP22

D

V

O

B

_

H

SYN

C

DV

OB

_V

S

Y

NC

RS

T

_

DV

I

DV

OB

_D0

DV

OB

_D1

DVOB_D23

DVOB_D13
DVOB_D12

DVOB_D21

DVOB_D18

DVOB_D11

DV

OB

_D7

DV

OB

_D2

DVOB_D17

DVOB_D9

DV

OB

_D6

DVOB_D15

DVOB_D22

DVOB_D10

DVOB_D8

DVOB_D14

DVOB_D16

DVOB_D20
DVOB_D19

DV

OB

_D3

DV

OB

_CLK

1

DV

OB

_CLK

0

DV

OB

_D5

DV

OB

_D4

HSOUT_S

(1,3)

VSYNCOUT_S

(1,3)

RP_D[7..0]

(1,3)

DATACLK_S

(1,3)

XTALCLKOUT

(1)

CY_CLKOUT

(7)

DATACLKB_S

(1,3)

BS_D[7..0]

1,3)

ADDR[0..15]

(7)

DATA[0..7] (7)

WR# (7)
RD# (7)

DVOB_D[0..23]

(6)

DVOB_CLK0 (6)
DVOB_CLK1 (6)
DVOB_BLANK (6)
DVOB_HSYNC

(6)

DVOB_VSYNC (6)

TDI (4)
TMS (4)
TCK (4)
TDO (4)

CY_PROG (4,7)
CY_CLK (4,7)
CY_DIN0

(4,7)

CY_DIN1

(7)

CY_INITB (4,7)
CY_DONE (4,7)
CY_BUSY

(7)

GP_D[7..0]

(1,3)

BP_D[7..0]

(1,3)

GS_D[7..0]

(1,3)

RS_D[7..0]

(1,3)

RST_DVI_MASTER (6)

SP14 (7)

SP15

(7)

SP17

(7)

SP19

(7)

SP27

(7)

SP13

(7)

SP25

(7)

SP23

(7)

SP21

(7)

SP12 (7)

SP28 (7)

SP26 (7)

SP24 (7)

SP22 (7)

SP20 (7)

SP18 (7)

SP16 (7)

HSYNCOUT_S

(1,3)

VSOUT_S

(1,3)

3.3V

2.5V

3.3V

3.3V

1.2V

3.3V

3.3V

R58

0

R194

100

R196

100

U20A

XC3S400_PQ208

4
5
7
9

10
11
12
13

15
16
18
19
20
21
22
24

29

31

33
34
35
36

37
39
40
42
43
44

46

45

48
50

57

58

61

62

63

64

65

67

68

71

72

74

76

77

78

79

81

83

85

86

87

90

92

80

93

94

95

96

97

101

100

117
116
115
114
113
111
109
108

128
126
125
124
123
122
120
119

139
138
137
135
133
132
131
130

149
148
147
146
144
143
141
140

172

171

175

169

168

167

166

165

191

190

198

189

187

185

182

178

204

203

200

197

176

196

199

194

207

206

205

201

188

164
177

6

23
32
49

136

153

110

127

84

98

60

73

208

159

160

158

180

181

183

184

2
3

51
52

54

55

56

102

103

104

26
27
28

106

107

155

156

150

154
152

161

162

I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O

I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O

I/O

I/O

I/O
I/O
I/O
I/O

I/O
I/O
I/O
I/O
I/O
I/O

I/O

I/O

I/O
I/O

I/O

_

C

S_

B

I/

O

_RDWR_B

DCI

_51

DCI

_52

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

_

B

U

S

Y

I/O

_

IN

IT_

B

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

DCI

_42

DCI

_41

I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O

I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O

I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O

I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

P

R

OG_B

H

S

W

A

P_

EN

I/O

Vcco_02

Vcco_01

Vcco_11
Vcco_12

Vcco_71
Vcco_72
Vcco_61
Vcco_62

Vcco_21

Vcco_22

Vcco_31

Vcco_32

Vcco_41

Vcco_42

Vcco_51

Vcco_52

TD

I

TC

K

TMS

TD

O

CLK

0

/I

CLK

1

/I

CLK

2

/I

CLK

3

/I

DCI_71
DCI_72

DCI_61
DCI_62

M1

M0

M2

I/O

DONE

CCLK

I/O
I/O
I/O

DCI_31

DCI_32

DCI_21

DCI_22

I/O

I/O
I/O

DCI

_11

DCI

_12

R197

100

JP42

1

2

3

4

5

6

JP5

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

R193

10K

R192

10K

R191

10K

JP39

XILINX-JTAG FPGA

1
2
3
4
5
6
7
8
9

U20B

XC3S400_PQ208

8

1

14
25
30
41
47
53
59
66
75
82
91
99

105
112
118
129
134
145
151
157
163
170
179
186
195
202

17
38
69
89

121
142
173
193

70

88

174

192

GND

GND

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

VCCAUX
VCCAUX
VCCAUX
VCCAUX

VCCAUX
VCCAUX
VCCAUX
VCCAUX

VCCINT

VCCINT

VCCINT

VCCINT

R195

100

Summary of Contents for ISL98001

Page 1: ...ration 1001 Murphy Ranch Rd Milpitas CA 95035 Tel 408 432 8888 http www intersil com 2005 Intersil Corp Page 1 16 Ver 1 1 12 19 05 Installation and Operation of Intersil s ISL98001 Analog Front End Evaluation System ...

Page 2: ... and ME not currently supported Hardware Requirements USB Port CD ROM drive for install files minimum 10MB free hard disk space Software Installation Launch the ISL98001 Installer exe file on the CD ROM and follow the instructions The default installation will add an Intersil directory to the Start Menu Programs tree That directory will contain a shortcut to the ISL98001 executable and an uninstal...

Page 3: ... Tel 408 432 8888 http www intersil com 2005 Intersil Corp Page 3 16 Ver 1 1 12 19 05 By default the installer will put the evaluation software under c Program Files ISL98001 directory To us a different directory select the Browse button Press Next to continue ...

Page 4: ...nch Rd Milpitas CA 95035 Tel 408 432 8888 http www intersil com 2005 Intersil Corp Page 4 16 Ver 1 1 12 19 05 Press Next to create the Intersil folder in the Start Menu Press the Install button to copy all the necessary files onto the PC ...

Page 5: ...he provided 5V power supply Connect the USB cable to the ISL98001 Evaluation Board The Microsoft windows operating system will see the ISL98001 Evaluation Board as a new device and will try to load appropriate driver for it Windows XP may pop up this message If you see this box select Yes now and every time I connect a device and click on Next If you elect not to select Yes now and every time I co...

Page 6: ... 95035 Tel 408 432 8888 http www intersil com 2005 Intersil Corp Page 6 16 Ver 1 1 12 19 05 The following screen will then appear Press Next Install the software automatically The Hardware Wizard will try to locate and install the driver for the ISL98001 ...

Page 7: ... Ranch Rd Milpitas CA 95035 Tel 408 432 8888 http www intersil com 2005 Intersil Corp Page 7 16 Ver 1 1 12 19 05 Click Finish to complete the installation On XP systems a pop up message may display the status of the ISL98001 hardware ...

Page 8: ...y operation is this Connect a monitor with a DVI input to the DVI output connector Connect a 1280x1024 60Hz RGB video source to VGA1 Connect the 5V power supply to the power connector At this point the evaluation board s FPGA will format the data from the ISL98001 and generate SXGA video timing on the DVI output connector The incoming SXGA image should appear on the DVI monitor Additional video mo...

Page 9: ...ault location is Start Programs Intersil ISL98001 After the program has launched you should see the following screen Click on the Read All Registers button in the lower left screen All of the register values from the ISL98001 on the evaluation board should appear as shown in the next image If the register values are not read correctly proceed to the Troubleshooting section of this document ...

Page 10: ...box then quickly type both digits of the desired value If you type too slowly more than 1 second between the first and second digit the first digit typed will become the lower nibble and the higher nibble will be 0 To only change one nibble using the keyboard select the high nibble or the low nibble and type the new hexadecimal value You can also change the register values using the keyboard Incre...

Page 11: ...ion platform does not automatically detect the video mode of the incoming video signal To obtain the correct image on the DVI monitor the software needs to be told the format of the incoming video signal This is done using the Video Mode box which is opened by selecting Select Input Video Mode from the options menu Using the drop down menu select the resolution and refresh rate that matches the re...

Page 12: ...ere is a composite video connection the ISL98001 AFE does not support composite video decoding It will simply digitize the composite video signal through the AFE s video channel It is possible to take that digitized composite signal and perform digital decoding of the composite signal after it is digitized but that is beyond the function of this evaluation system ...

Page 13: ... control The Automatic Black Level Compensation ABLC register 0x17 function can be disabled to compare the image with and without ABLC Please refer to the ISL98001 datasheet for more information on the ISL98001 and its configuration options Notes All registers can be read by pressing the Read All Registers button Registers 0x00 0x02 are read only The HTOTAL value is not latched by the ISL98001 unt...

Page 14: ...CA 95035 Tel 408 432 8888 http www intersil com 2005 Intersil Corp Page 14 16 Ver 1 1 12 19 05 DE Adjust If the image on the DVI monitor is clipped the following window allows the Data Enable DE signal to be adjusted to change the position of the frame ...

Page 15: ...e evaluation board as soon as it is launched If there is a communication problem the following dialog box will be displayed If you see this dialog open the Windows Control Panel Double click on the System icon and select the Hardware tab then click on Device Manager There should be a Jungo entry with an ISL98001 sub category This indicates the driver is properly installed and is communicating with...

Page 16: ...oard and software Note The ISL98001 Evaluation Board has a Vendor ID VID of 0x09AA and Product ID PID of 0x1004 If the USB connection is functioning but no image is displayed on the DVI monitor take the following steps Make sure the input video mode resolution refresh rate matches the Input Video Mode selection in the software Close the software reset the ISL98001 reset the microcontroller and res...

Page 17: ...75 C13 0 01uF VSin2 1 Y1 25 Mhz RP13 33 Ohm 1 2 3 4 5 6 7 8 C9 22pF R156 0 Ohm R5 4 7K C15 0 01uF HSin2 1 RP14 33 Ohm 1 2 3 4 5 6 7 8 JP24 1 2 C10 22pF VS2 1 RP5 33 Ohm 1 2 3 4 5 6 7 8 C17 0 01uF U1 X98001LC 7 12 14 19 13 22 24 26 28 25 33 44 34 45 41 46 55 56 57 58 59 60 61 62 75 74 73 72 71 70 69 68 87 86 85 84 83 81 82 80 90 91 92 93 94 95 96 97 100 101 102 103 104 105 106 107 112 113 114 115 1...

Page 18: ...EXT 1 RGBgnd2 1 R_IN_2 1 5V_VGA2 AVdd_3 3V 5V 5V 5V PB1 1 J10C RCA_COM 3 6 R177 75 J9A RCA_COM 1 2 R174 75 C5 0 1uF PR2 1 R175 75 R9 75 COMPS1 1 R30 20K C6 0 1uF R31 10K R173 75 Y2 1 R15 75 R32 100K U23 EL4511CU 1 2 3 4 5 6 7 8 9 10 11 12 13 15 24 14 16 17 18 20 19 21 22 23 XTAL VBLANK SYNCLOCK PDWN SDENB SCL SDA GNDD1 HIN SYNCIN VERTIN LEVEL GNDA1 VCCA2 XTALN VCCA1 GNDA2 GNDD2 VCCD BACKPORCH SYNC...

Page 19: ...RS_D0 RS_D2 RS_D3 RP_D 7 0 1 5 GP_D 7 0 1 5 GS_D 7 0 1 5 BP_D 7 0 1 5 BS_D 7 0 1 5 DATACLK_S 1 5 DATACLKB_S 1 5 HSOUT_S 1 5 VSOUT_S 1 5 HSYNCOUT_S 1 5 VSYNCOUT_S 1 5 DDC_SDA2 2 DDC_SCL2 2 DDC_SDA1 1 DDC_SCL1 1 RS_D 7 0 1 5 DATACLK_S 1 5 5V_VGA1 5V_VGA2 U4 24LC02 SMT 1 2 3 4 5 6 7 8 A0 A1 A2 Gnd SDA SCL WP VCC U3 24LC02 SMT 1 2 3 4 5 6 7 8 A0 A1 A2 Gnd SDA SCL WP VCC R26 4 7K HDR23 HEADER 8x2 SM 1 ...

Page 20: ...100 C168 0 01uF R48 390 D9 LED C32 10uF 1 2 C65 0 1uF C11 0 1uF TP5 1 C77 0 1uF C35 47uF 1 2 C53 0 1uF C58 0 1uF C79 0 1uF C64 0 1uF C167 22uF 1 2 C166 0 1uF R47 240 R163 330 TP6 1 C73 0 1uF C23 0 1uF C68 0 1uF C75 0 1uF C57 0 1uF R42 0 Ohm C78 0 1uF C55 0 1uF SW3 C63 0 1uF U29 LM1117 1 2 3 4 ADJ Vo2 Vin Vo4 C36 0 1uF R152 1K U32 XCF02S_VO20 1 2 9 12 14 15 16 11 20 19 18 13 10 3 4 5 6 7 8 17 D0 NC...

Page 21: ...RST_DVI_MASTER 6 SP14 7 SP15 7 SP17 7 SP19 7 SP27 7 SP13 7 SP25 7 SP23 7 SP21 7 SP12 7 SP28 7 SP26 7 SP24 7 SP22 7 SP20 7 SP18 7 SP16 7 HSYNCOUT_S 1 3 VSOUT_S 1 3 3 3V 2 5V 3 3V 3 3V 1 2V 3 3V 3 3V R58 0 R194 100 R196 100 U20A XC3S400_PQ208 4 5 7 9 10 11 12 13 15 16 18 19 20 21 22 24 29 31 33 34 35 36 37 39 40 42 43 44 46 45 48 50 57 58 61 62 63 64 65 67 68 71 72 74 76 77 78 79 81 83 85 86 87 90 9...

Page 22: ... DVI_TX0 DVI_TXC DVI_TXC 3 3V 3 3V 3 3V 5V C82 10uF C91 10uF 1 2 C81 0 1uF C86 0 1uF C89 10uF FB1 U11 SiI164 11 10 13 15 14 9 34 35 36 37 38 39 40 41 42 43 44 45 46 47 50 51 52 53 54 55 58 59 60 61 62 63 4 5 2 57 8 7 6 56 19 31 30 28 27 25 24 22 21 23 29 20 26 32 16 17 48 64 18 49 1 12 33 3 MSEN SOUT PD ISEL RST BSEL SCL DSEL SDA EDGE CHG RESERVED GND D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 SYNCO ...

Page 23: ...2 23 105 106 107 108 114 115 116 117 118 120 121 122 127 128 1 2 34 33 41 25 26 27 28 29 30 31 32 79 80 81 82 83 84 85 86 110 111 112 113 123 124 125 126 48 17 36 55 35 37 39 40 47 52 7 65 66 49 53 54 62 67 56 57 58 59 60 61 63 64 88 89 90 91 92 93 94 95 24 101 96 97 100 109 73 74 119 76 77 87 99 70 71 72 78 68 75 102 103 104 44 45 46 D0 D1 D2 D3 D4 D5 D6 D7 VCC AVCC SCL SDA XIN NCN42 NCN43 RSV50 ...

Page 24: ......

Page 25: ......

Page 26: ......

Page 27: ......

Page 28: ......

Page 29: ......

Reviews: